VXIMonitor Subsystem

3.Query operation register to check if either D5, D8, D9 or D10 are set. STAT:OPER?

The system response: 288 (0 x 120 ± VXI Triggers set and VXI Monitor)

4.Since the VXI Trigger bit was set, now query the Trigger register. STAT:OPER:VXIT?

The system response: 16 (0 x 10 ± TTL4 Trigger occurred).

5.Query the time that TTL Trigger line 4 triggered. STAT:OPER:VXIT:TRIG? TTL4

The system response: 0,34,30 (Trigger occurred on line TTL4 34.5 minutes after power on).

6.When the ªSTAT:OPER?º query was performed, the VXI Monitor bit was also set. Use the following command to examine specifically what event occurred.

STAT:OPER:VXIM?

The system response: 3 (BERR and SYSFAIL are set).

7.STAT:OPER:VXIM:BERR?

The system response: A16 (Bus Error occurred in A16 address space).

8.STAT:OPER:VXIM:SYSF?

The system response: 1, 30, 0 (SYSFAIL occurred one and one-half hours after power-up)

NOTE. If this test were run with the VXI Monitor enable register set to zero (ªSTAT:OPER:VXIM:ENABLE 0º), the VXI Monitor bit would not be set in the operation register. However, if the VXI Monitor enable register was set to 0 x F (ªSTAT:OPER:VXIT:ENABLE 15º), then only triggers on TTL0, TTL1, TTL2 and TTL3 lines will cause the VXIT trigger bit to be set in the operation register (ªSTAT:OPER?º). The VXI Trigger register (ªSTAT:OPER:VXIT?º) will always show all Trigger lines that are triggered, regardless of the setting in the enable register.

3±156

VX1410A & VX1420A IntelliFrame Mainframe Instruction Manual