Agilent Technologies 6813B Status Byte Register, Examples, Command Action, The MSS Bit, Step

Programming Examples - 4

Status Byte Register

This register summarizes the information from all other status groups as defined in the IEEE 488.2 Standard Digital Interface for Programmable Instrumentation. The bit configuration is shown in Table 4-1.

Command Action

*STB? - reads the data in the register but does not clear it (returns MSS in bit 6) serial poll - reads and clears the data in the register (returns RQS in bit 6)

The MSS Bit

This is a real-time (unlatched) summary of all Status Byte register bits that are enabled by the Service Request Enable register. MSS is set whenever the ac source has one or more reasons for requesting service. *STB? reads the MSS in bit position 6 of the response but does not clear any of the bits in the Status Byte register.

The RQS Bit

The RQS bit is a latched version of the MSS bit. Whenever the ac source requests service, it sets the SRQ interrupt line true and latches RQS into bit 6 of the Status Byte register. When the controller does a serial poll, RQS is cleared inside the register and returned in bit position 6 of the response. The remaining bits of the Status Byte register are not disturbed.

The MAV bit and Output Queue

The Output Queue is a first-in, first-out (FIFO) data register that stores ac source-to-controller messages until the controller reads them. Whenever the queue holds one or more bytes, it sets the MAV bit (4) of the Status Byte register.

Examples

Determining the Cause of a Service Interrupt

You can determine the cause for an SRQ by the following actions:

Step 1 Determine which summary bits are active. Use:

*STB? or

serial poll

Step 2

Step 3

Read the corresponding Event register for each summary bit to determine which events caused the summary bit to be set. Use:

STATus:QUEStionable:EVENt?

STATus:OPERation:EVENt?

ESR?

When an Event register is read, it is cleared. This also clears the corresponding summary bit.

Remove the specific condition that caused the event. If this is not possible, the event may be disabled by programming the corresponding bit of the status group Enable register or NTRPTR filter. A faster way to prevent the interrupt is to disable the service request by programming the appropriate bit of the Service Request Enable register.

147