Introduction to State Analysis
State analysis in its simplest form means acquiring data and storing it when it is valid for a system under test. When doing state analysis, you must put the analyzer into state mode. The differences between state mode and timing mode are the source of the sample clock and the way the data is displayed. In state analysis, the source of the sample clock is the system under test, rather than the analyzer, and the default display is a sequential listing of logical states, rather than a waveform.
Each time the analyzer receives a state clock pulse, it samples and stores the logic state of the system under test. Just as in the timing analyzer, the state analyzer compares sampled data to a threshold voltage to determine whether it should be stored and displayed as a logic high or a logic low. The analyzer then displays the data as a sequential listing of logical states.
What makes the analyzer more than just a data acquisition instrument is its capability to acquire and store only the data that you specify. This is called data qualification. Examples of storing qualified data include storing only a certain subroutine in a program, storing all data being sent to a specified address in a system, or storing only data leading up to a system failure.
In this chapter, you will:
•Put the analyzer into state mode
•Set up the state clock
•Change a label name and modify channel assignments
•Define a term for the state trigger
•Set up the trigger specification
•Run the analyzer and view and change the state listing
•Create and view symbols