TEST:TST[:RESults]?, 102

calibration connections (CAL), 158

*TST?, 103

calibration connections (CHAN), 158

*TRG, 106

calibration path, querying, 77

Trigger

calibration path, setting, 76

channels, 104

calibration status register, 144

control register, 131–132

channel output connections, 33

external, 54

channel output connections, combining, 34, 57

external connections, 35

channel output connections, querying, 92, 94

idle state, 80

channel output connections, specifying, 65, 91, 93

ignored interrupt condition, 133

channel output mode, 13, 45, 89

immediate, 54

DC specifications, 111

process, 55

gain calibration constant, 141

query current status, 79

mode calibration, 72, 74–75

setting, 54–55

offset calibration constant, 140

software, 54

output adjustment, 154–165

source, querying, 105

VTL, 40, 47

source, setting, 105

VXI

status for channels, 135

offset register, 128

system, ABORt command, 63

status/control register, 127–128

system, INITiate command, 80

VXIbus, 13

system, TRIGger commands, 104–105

backplane circuitry, 17

VXIbus backplane, 54, 81–82, 132

backplane trigger, 54, 81–82, 132

wait-for-trigger state, 80

SYSFAIL* line, 127–128

TRIGger Subsystem, 104–105

TTLTRG line, 81–82, 131–132

TRIGger:SOURce, 54–55, 105

word serial protocol, 113

TRIGger:SOURce?, 105

 

Triggering, 54–55

W

Troubleshooting, 173

 

*TST?, 53, 103, 106, 173

*WAI, 106

TTLTRG Line, 81–82, 131–132

Wait-for-Trigger State, 80

Two-wire Connections, 33

WARNINGS, 8

 

Warranty, 7

U

Wiring Terminal Module, 23–24

 

Writing To

Undefined Registers, 140

calibration card configuration register, 147

Using

calibration checksum register, 147

*OPC?, 56

calibration control register, 129

trigger control register, 132

calibration isolation status register, 146

 

calibration resistor value registers, 144

V

card control register, 137

 

channel current gain calibration registers, 143

V/I Jumper, 17, 31, 52

channel current offset calibration registers, 142

option A3E, 32

channel mode register, 136

option A3H, 32

channel relay control register, 136

VI_SUCCESS, 47

channel voltage gain calibration registers, 141

viPrintf, 40, 47

channel voltage offset calibration registers, 140

VISA Transition Library

current calibration status register, 145

See VTL

Gain_DAC registers, 139

visa.h, 39

interrupt status register, 133

viScanf, 40

logical address register, 126

ViStatus, 47

Main_DAC immediate registers, 138

Voltage

Main_DAC triggered registers, 138

adjustment, 157–158

non-volatile (FLASH) memory, 140–143, 155

185 HP E1418A User’s Manual

Page 185
Image 185
HP E1418A manual See VTL