Interrupt Status Register
The Interrupt Status Register shows the state of the trigger ignored interrupt condition. The bit is a strobed interrupt source.
Bit | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 |
Address
Base + 1216 READUnusedTRGUnused
WRITE
IGN
Isolation Status Register
TRG IGN: This field is set to a one (1) if the trigger ignored condition exists.
The Isolation Status Register reports the
Address | Bit | 15 | 14 | 13 | 12 | 11 | 10 | 09 | 08 | 07 | 06 | 05 | 04 | 03 | 02 | 01 | 00 | |
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READ | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | Ch | ||
Base + 1416 | ||||||||||||||||||
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| ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | ISO | |
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Ch XX ISO: Each field will return a one (1) if the channel has a
Notes A channel will not function without a
For
Appendix B | HP E1418A |