Intel E5-1600, CM8062101038606 Peci Signal, System Reference Clock Signals, Jtag and TAP Signals

Signal Descriptions

6.5PECI Signal

Table 6-10. PECI Signals

Signal Name

PECI

Description

PECI (Platform Environment Control Interface) is the serial sideband interface to the processor and is used primarily for thermal, power and error management. Details regarding the PECI electrical specifications, protocols and functions can be found in the Platform Environment Control Interface Specification.

6.6System Reference Clock Signals

Table 6-11. System Reference Clock (BCLK{0/1}) Signals

Signal Name	Description
BCLK{0/1}_D[N/P]	Reference Clock Differential input. These pins provide the PLL reference clock
	differential input into the processor. Both 100MHz BCLK0 and BCLK1 from the same
	clock source provide the required reference clock inputs to the various PLLs inside
	the CPU.

6.7JTAG and TAP Signals

Table 6-12. JTAG and TAP Signals

Signal Name

BPM_N[7:0]

Description

Breakpoint and Performance Monitor Signals: I/O signals from the processor that indicate the status of breakpoints and programmable counters used for monitoring processor performance. These are 100 MHz signals.

EAR_N	External Alignment of Reset, used to bring the processor up into a deterministic state.
	This signal is pulled up on the die, refer to Table 7-6for details.
PRDY_N	Probe Mode Ready is a processor output used by debug tools to determine processor
	debug readiness.
PREQ_N	Probe Mode Request is used by debug tools to request debug operation of the
	processor.
TCK	TCK (Test Clock) provides the clock input for the processor Test Bus (also known as the
	Test Access Port).
TDI	TDI (Test Data In) transfers serial test data into the processor. TDI provides the serial
	input needed for JTAG specification support.
TDO	TDO (Test Data Out) transfers serial test data out of the processor. TDO provides the
	serial output needed for JTAG specification support.
TMS	TMS (Test Mode Select) is a JTAG specification support signal used by debug tools.
TRST_N	TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be driven
	low during power on Reset.

Note: Refer to the appropriate Platform Design Guide (PDG) for Debug Port implementation details.

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families	147
Datasheet Volume One