Main
Page
Contents
Page
Page
Figures
Page
Tables
Page
Page
Page
Page
1
1.1 Introduction
1.1.1 Processor Feature Details
1.1.2 Supported Technologies
1.2 Interfaces
1.2.1 System Memory Support
1.2.2 PCI Express*
Page
1.2.3 Direct Media Interface Gen 2 (DMI2)
1.2.4 Intel QuickPath Interconnect (Intel QPI)
1.2.5 Platform Environment Control Interface (PECI)
1.3 Power Management Support
1.3.1 Processor Package and Core States
1.3.2 System States Support
1.3.3 Memory Controller
1.3.4 PCI Express
1.4 Thermal Management Support
1.5 Package Summary
1.6 Terminology
Page
Page
1.7 Related Documents
Refer to the following documents for additional information.
Table 1-1. Referenced Documents (Sheet 1 of 2)
1.8 State of Data
2
2.1 System Memory Interface
2.1.1 System Memory Technology Support
2.1.2 System Memory Timing Support
Page
2.2.1.1 Transaction Layer
2.2.1.2 Data Link Layer
2.2.1.3 Physical Layer
2.2.2 PCI Express* Configuration Mechanism
Framing Sequence Number Header Data LCRCECRC Framing Transaction Layer Physical Layer
Data Link Layer
2.3 DMI2/PCI Express* Interface
2.3.1 DMI2 Error Flow
2.3.2 Processor/PCH Compatibility Assumptions
2.3.3 DMI2 Link Down
2.4 Intel QuickPath Interconnect
Page
2.5 Platform Environment Control Interface (PECI)
2.5.1 PECI Client Capabilities
2.5.1.1 Thermal Management
2.5.1.2 Platform Manageability
2.5.1.3 Processor Interface Tuning and Diagnostics
2.5.2 Client Command Suite
2.5.2.1 Ping()
An example Ping() command to PECI device address 0x30 is shown below.
2.5.2.2 GetDIB()
Figure 2-3. Ping()
Figure 2-4. Ping() Example
Byte # Byte Definition
0 0x30
Reserved # of Domains Reserved
Byte# 5
Byte# 6
Major Revision# Minor Revision#
2.5.2.3 GetTemp()
2.5.2.4 RdPkgConfig()
2.5.2.5 WrPkgConfig()
Page
2.5.2.6 Package Configuration Capabilities
Page
Page
Page
Page
Page
Page
Page
Services Summary (Sheet 1 of 3)
Services Summary (Sheet 2 of 3)
Services Summary (Sheet 3 of 3)
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
Page
2.5.2.7 RdIAMSR()
Page
Page
Table 2-11. RdIAMSR() Services Summary (Sheet 2 of 2)
2.5.2.8 RdPCIConfig()
2.5.2.9 RdPCIConfigLocal()
DeviceBus Function Register
Page
2.5.2.10 WrPCIConfigLocal()
Figure 2-48. WrPCIConfigLocal()
Table 2-14. WrPCIConfigLocal() Response Definition
2.5.3 Client Management
2.5.3.1 Power-up Sequencing
2.5.3.2 Device Discovery
2.5.3.3 Client Addressing
2.5.3.4 C-states
2.5.3.5 S-states
2.5.3.6 Processor Reset
2.5.3.7 System Service Processor (SSP) Mode Support
2.5.3.8 Processor Error Handling
2.5.3.9 Originator Retry and Timeout Policy
2.5.3.10 Enumerating PECI Client Capabilities
2.5.4 Multi-Domain Commands
2.5.5 Client Responses
2.5.5.1 Abort FCS
2.5.5.2 Completion Codes
2.5.6 Originator Responses
2.5.7 DTS Temperature Data
2.5.7.1 Format
2.5.7.2 Interpretation
2.5.7.3 Temperature Filtering
TN = (1-) * TN-1 + * TSAMPLE
= 1/2X, where X is the Thermal Averaging Constant that is programmable as
2.5.7.4 Reserved Values
Page
3
3.1 Intel Virtualization Technology (Intel VT)
3.1.1 Intel VT-x Objectives
3.1.2 Intel VT-x Features
3.1.3 Intel VT-d Objectives
3.1.3.1 Intel VT-d Features Supported
3.1.4 Intel Virtualization Technology Processor Extensions
3.2 Security Technologies
3.2.1 Intel Trusted Execution Technology
3.2.2 Intel Trusted Execution Technology Server Extensions
3.2.3 Intel Advanced Encryption Standard Instructions (Intel AES-NI)
3.2.4 Execute Disable Bit
3.3 Intel Hyper-Threading Technology
3.4 Intel Turbo Boost Technology
3.4.1 Intel Turbo Boost Operating Frequency
3.5 Enhanced Intel SpeedStep Technology
3.6 Intel Intelligent Power Technology
3.7 Intel Advanced Vector Extensions (Intel AVX)
3.8 Intel Dynamic Power Technology (Intel DPT)
Page
4
4.1 ACPI States Supported
4.1.1 System States
4.1.2 Processor Package and Core States
4.1.3 Integrated Memory Controller States
Table 4-2. Package C-State Support (Sheet 2 of 2)
Table 4-3. Core C-State Support
Table 4-4. System Memory Power States (Sheet 1 of 2)
4.1.4 DMI2/PCI Express Link States
4.1.5 Intel QuickPath Interconnect States
4.1.6 G, S, and C State Combinations
Table 4-5. DMI2/PCI Express* Link States
Table 4-4. System Memory Power States (Sheet 2 of 2)
4.2 Processor Core/Package Power Management
4.2.1 Enhanced Intel SpeedStep Technology
4.2.2 Low-Power Idle States
4.2.3 Requesting Low-Power Idle States
Core 0 State
C1 C1E C7C6C3
Core N State
Processor Package State
4.2.4 Core C-states
4.2.4.1 Core C0 State
4.2.4.2 Core C1/C1E State
4.2.4.3 Core C3 State
4.2.4.4 Core C6 State
4.2.4.5 Core C7 State
4.2.4.6 C-State Auto-Demotion
4.2.5 Package C-States
4.2.5.1 Package C0
C2
4.2.5.2 Package C1/C1E
C6C3
C0 C1
4.2.5.3 Package C2 State
4.2.5.4 Package C3 State
4.2.5.5 Package C6 State
4.2.6 Package C-State Power Specifications
4.3 System Memory Power Management
4.3.1 CKE Power-Down
4.3.2 Self Refresh
4.3.2.1 Self Refresh Entry
4.3.2.2 Self Refresh Exit
4.3.2.3 DLL and PLL Shutdown
4.4 DMI2/PCI Express* Power Management
Page
5
Specifications
5.1 Package Thermal Specifications
5.1.1 Thermal Specifications
5.1.2 TCASE and DTS Based Thermal Specifications
Page
5.1.3 Processor Thermal Profiles
5.1.3.1 8-Core 150W Thermal Specifications
Table 5-1. Processor SKU Summary Table
Table 5-2. Tcase: 8-Core 150W Thermal Specifications, Workstation Platform SKU Only
Figure 5-1. Tcase: 8-Core 150W T h ermal Profile, Workstation Platform SKU Only
Figure 5-2. DTS: 8-Core 150W Thermal Profile, Workstation Platform SKU Only
Table 5-3. 8-Core 150W Thermal Profile, Workstation Platform SKU Only
5.1.3.2 8-Core 135W Thermal Specifications
Table 5-4. Tcase: 8-Core 135W Thermal Specifications 2U
Figure 5-3. Tcase: 8-Core 135W Thermal Profile 2U
Figure 5-4. DTS: 8-Core 135W Thermal Profile 2U
Table 5-5. 8-Core 135W Thermal Profile Table 2U (Sheet 1 of 2)
5.1.3.3 8/6-Core 130W Thermal Specifications
Table 5-6. Tcase: 8/6-Core 130W Thermal Specifications, Workstation/Server Platform
Table 5-5. 8-Core 135W Thermal Profile Table 2U (Sheet 2 of 2)
Figure 5-5. Tcase: 8/6-Core 130W Thermal Profile 1U
Figure 5-6. DTS: 8-Core 130W Thermal Profile 1U
Figure 5-7. DTS: 6-Core 130W Thermal Profile 1U
Table 5-7. 8/6-Core 130W Thermal Profile Table 1U (Sheet 1 of 2)
5.1.3.4 6-Core 130W 1S WS Thermal Specifications
Table 5-8. Tcase: 6-Core 130W 1S WS Thermal Specifications
Figure 5-8. Tcase: 6-Core 130W 1S WS Thermal Profile
Table 5-7. 8/6-Core 130W Thermal Profile Table 1U (Sheet 2 of 2)
Figure 5-9. DTS: 6-Core 130W 1S WS Thermal Profile
Table 5-9. 6-Core 130W 1S WS Thermal Profile Table (Sheet 1 of 2)
5.1.3.5 8-Core 115W Thermal Specifications
Table 5-10. Tcase: 8-Core 115W Thermal Specifications 1U
Table 5-9. 6-Core 130W 1S WS Thermal Profile Table (Sheet 2 of 2)
Figure 5-10. Tcase: 8-Core 115W Thermal Profile 1U
Figure 5-11. DTS: 8-Core 115W Thermal Profile 1U
5.1.3.6 8/6-Core 95W Thermal Specifications
Table 5-11. 8-Core 115W Thermal Profile Table 1U
Table 5-12. Tcase: 8/6-Core 95W Thermal Specifications, Workstation/Server Platform
Figure 5-12. Tcase: 8/6-Core 95W Thermal Profile 1U
Figure 5-13. DTS: 8-Core 95W Thermal Profile 1U
Figure 5-14. DTS: 6-Core 95W Thermal Profile 1U
Table 5-13. 8/6-Core 95W Thermal Profile Table 1U (Sheet 1 of 2)
5.1.3.7 8-Core 70W Thermal Specifications
Table 5-14. Tcase: 8-Core 70W Thermal Specifications 1U
Figure 5-15. Tcase: 8-Core 70W Thermal Profile 1U
Table 5-13. 8/6-Core 95W Thermal Profile Table 1U (Sheet 2 of 2)
Figure 5-16. DTS: 8-Core 70W Thermal Profile 1U
Table 5-15. 8-Core 70W Thermal Profile Table 1U
5.1.3.8 6-Core 60W Thermal Specifications
Table 5-16. Tcase: 6-Core 60W Thermal Specifications 1U
Figure 5-17. Tcase: 6-Core 60W Thermal Profile 1U
Figure 5-18. DTS: 6-Core 60W Thermal Profile 1U
Table 5-17. 6-Core 60W Thermal Profile Table 1U
5.1.3.9 4-Core 130W Thermal Specifications
Table 5-18. Tcase: 4-Core 130W Thermal Specifications 2U
Figure 5-19. Tcase: 4-Core 130W Thermal Profile 2U
Figure 5-20. DTS: 4-Core 130W Thermal Profile 2U
Table 5-19. 4-Core 130W Thermal Profile Table 2U (Sheet 1 of 2)
5.1.3.10 4-Core 130W 1S WS Thermal Specifications
Table 5-20. Tcase: 4-Core 130W 1S WS Thermal Specifications, Workstation/Server Platform
Table 5-19. 4-Core 130W Thermal Profile Table 2U (Sheet 2 of 2)
Figure 5-21. Tcase: 4-Core 130W 1S WS Thermal Profile
Figure 5-22. DTS: 4-Core 130W 1S WS Thermal Profile
5.1.3.11 4-Core 95W Thermal Specifications
Table 5-21. 4-Core 130W 1S WS Thermal Profile Table
Table 5-22. Tcase: 4-Core 95W Thermal Specifications 1U
Figure 5-23. Tcase: 4-Core 95W Thermal Profile 1U
Figure 5-24. DTS: 4-Core 95W Thermal Profile 1U
5.1.3.12 4/2-Core 80W Thermal Specifications
Table 5-23. 4-Core 95W Thermal Profile Table 1U
Table 5-24. Tcase: 4/2-Core 80W Thermal Specifications 1U
Figure 5-25. Tcase: 4/2-Core 80W Thermal Profile 1U
Figure 5-26. DTS: 4-Core 80W Thermal Profile 1U
Figure 5-27. DTS: 2-Core 80W Thermal Profile 1U
Table 5-25. 4/2-Core 80W Thermal Profile Table 1U (Sheet 1 of 2)
5.1.4 Embedded Server Processor Thermal Profiles
5.1.4.1 8-Core LV95W Thermal Specifications
Figure 5-28. Tcase: 8-Core LV95W Thermal Profile, Embedded Server SKU
Figure 5-29. DTS: 8-Core LV95W Thermal Profile, Embedded Server SKU
Table 5-28. 8-Core LV95W Thermal Profiles, Embedded Server SKU (Sheet 1 of 2)
5.1.4.2 8-Core LV70W Thermal Specifications
Table 5-29. Tcase: 8-Core LV70W Thermal Specifications, Embedded Server SKU
Figure 5-30. Tcase: 8-Core LV70W Thermal Profile, Embedded Server SKU
Table 5-28. 8-Core LV95W Thermal Profiles, Embedded Server SKU (Sheet 2 of 2)
Figure 5-31. DTS: 8-Core LV70W Thermal Profile, Embedded Server SKU
Table 5-30. 8-Core LV70W Thermal Profile Table, Embedded Server SKU (Sheet 1 of 2)
5.1.5 Thermal Metrology
5.2 Processor Core Thermal Features
5.2.1 Processor Temperature
5.2.2 Adaptive Thermal Monitor
5.2.2.1 Frequency/SVID Control
5.2.2.2 Clock Modulation
5.2.3 On-Demand Mode
5.2.4 PROCHOT_N Signal
5.2.5 THERMTRIP_N Signal
5.2.6 Integrated Memory Controller (IMC) Thermal Features
5.2.6.1 DRAM Throttling Options
5.2.6.2 Hybrid Closed Loop Thermal Throttling (CLTT_Hybrid)
5.2.6.3 MEM_HOT_C01_N and MEM_HOT_C23_N Signal
5.2.6.4 Integrated Dual SMBus Master Controllers for SMI
6
6.1 System Memory Interface Signals
Table 6-1. Memory Channel DDR0, DDR1, DDR2, DDR3
6.2 PCI Express* Based Interface Signals
Note: PCI Express* Ports 1, 2 and 3 Signals are receive and transmit differential pairs.
Table 6-2. Memory Channel Miscellaneous
Table 6-3. PCI Express* Port 1 Signals
Table 6-4. PCI Express* Port 2 Signals (Sheet 1 of 2)
Table 6-5. PCI Express* Port 3 Signals
Table 6-6. PCI Express* Miscellaneous Signals (Sheet 1 of 2)
Table 6-4. PCI Express* Port 2 Signals (Sheet 2 of 2)
6.3 DMI2/PCI Express* Port 0 Signals
6.4 Intel QuickPath Interconnect Signals
Table 6-6. PCI Express* Miscellaneous Signals (Sheet 2 of 2)
Table 6-7. DMI2 and PCI Express* Port 0 Signals
Table 6-8. Intel QPI Port 0 and 1 Signals
6.5 PECI Signal
6.6 System Reference Clock Signals
6.7 JTAG and TAP Signals
Table 6-10. PECI Signals
Table 6-11. System Reference Clock (BCLK{0/1}) Signals
6.8 Serial VID Interface (SVID) Signals
6.9 Processor Asynchronous Sideband and Miscellaneous Signals
Table 6-13. SVID Signals
Table 6-14. Processor Asynchronous Sideband Signals (Sheet 1 of 3)
Table 6-14. Processor Asynchronous Sideband Signals (Sheet 2 of 3)
6.10 Processor Power and Ground Supplies
Table 6-15. Miscellaneous Signals
Table 6-16. Power and Ground Signals (Sheet 1 of 2)
Table 6-14. Processor Asynchronous Sideband Signals (Sheet 3 of 3)
Table 6-16. Power and Ground Signals (Sheet 2 of 2)
Page
7
7.1 Processor Signaling
7.1.1 System Memory Interface Signal Groups
7.1.2 PCI Express* Signals
7.1.3 DMI2/PCI Express* Signals
7.1.5 Platform Environmental Control Interface (PECI)
7.1.6 System Reference Clocks (BCLK{0/1}_DP, BCLK{0/ 1}_DN)
7.1.6.1 PLL Power Supply
7.1.7 JTAG and Test Access Port (TAP) Signals
7.1.8 Processor Sideband Signals
7.1.9 Power, Ground and Sense Signals
7.1.9.1 Power and Ground Lands
7.1.9.2 Decoupling Guidelines
7.1.9.3 Voltage Identification (VID)
Page
Page
Table 7-2. SVID Address Usage
Table 7-3. VR12.0 Reference Code Voltage Identification (VID) Table (Sheet 1 of 2)
7.1.10 Reserved or Unused Signals
7.2 Signal Group Summary
Table 7-5. Signal Groups (Sheet 1 of 3)
Table 7-4. Signal Description Buffer Types (Sheet 2 of 2)
Table 7-5. Signal Groups (Sheet 2 of 3)
Table 7-5. Signal Groups (Sheet 3 of 3)
7.3 Power-On Configuration (POC) Options
Table 7-6. Signals with On-Die Termination
Table 7-7. Power-On Configuration Option Lands
7.4 Fault Resilient Booting (FRB)
7.5 Mixing Processors
7.6 Flexible Motherboard Guidelines (FMB)
7.7 Absolute Maximum and Minimum Ratings
7.7.1 Storage Conditions Specifications
Page
7.8.1 Voltage and Current Specifications
Table 7-11. Voltage Specification
Table 7-12. Processor Current Specifications
I Core Supply, Processor Current on V
Table 7-13. 8/6 Core: Processor VCC Static and Transient Tolerance
Figure 7-3. 8/6-Core: VCC Static and Transient Tolerance Loadlines
Table 7-14. 4/2-Core: Processor VCC Static and Transient Tolerance (Sheet 1 of 2)
0-135 A for 95 W processor
Table 7-14. 4/2-Core: Processor VCC Static and Transient Tolerance (Sheet 2 of 2)
Electrical Specifications
Figure 7-4. 4/2-Core: Processor VCC Static and Transient Tolerance Loadlines
Vcc [V]
7.8.2 Die Voltage Validation
7.8.2.1 VCC Overshoot Specifications
7.8.3 Signal DC Specifications
VccMAX(I1)
0 5 10 15 20 25 30
Figure 7-6. VCC Overshoot Example Waveform
Table 7-15. VCC Overshoot Specifications (Sheet 2 of 2)
Table 7-16. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2)
Table 7-17. PECI DC Specifications
Table 7-18. System Reference Clock (BCLK{0/1}) DC Specifications
Table 7-19. SMBus DC Specifications (Sheet 1 of 2)
Table 7-20. JTAG and TAP Signals DC Specifications
Table 7-21. Serial VID Interface (SVID) DC Specifications (Sheet 1 of 2)
Table 7-19. SMBus DC Specifications (Sheet 2 of 2)
Table 7-22. Processor Asynchronous Sideband DC Specifications
Table 7-21. Serial VID Interface (SVID) DC Specifications (Sheet 2 of 2)
7.8.3.1 PCI Express* DC Specifications
7.8.3.2 DMI2/PCI Express* DC Specifications
7.8.3.3 Intel QuickPath Interconnect DC Specifications
7.8.3.4 Reset and Miscellaneous Signal DC Specifications
Figure 7-7. BCLK{0/1} Differential Clock Crosspoint Specification
0.0V
Figure 7-8. BCLK{0/1} Differential Clock Measurement Point for Ringback
REFCLK + V
T
250 + 0.5 (VHavg - 700)
7.9 Signal Quality
7.9.1 DDR3 Signal Quality Specifications
BCLK_DP
7.9.2 I/O Signal Quality Specifications
V
7.9.3 Intel QuickPath Interconnect Signal Quality Specifications
7.9.4 Input Reference Clock Signal Quality Specifications
7.9.5 Overshoot/Undershoot Tolerance
7.9.5.1 Overshoot/Undershoot Magnitude
7.9.5.2 Overshoot/Undershoot Pulse Duration
7.9.5.3 Activity Factor
7.9.5.4 Reading Overshoot/Undershoot Specification Tables
7.9.5.5 Determining if a System Meets the Overshoot/Undershoot Specifications
Page
8
8.1 Listing by Land Name
Table 8-1. Land Name (Sheet 1 of 49)
Table 8-1. Land Name (Sheet 2 of 49)
Table 8-1. Land Name (Sheet 3 of 49)
Table 8-1. Land Name (Sheet 4 of 49)
Table 8-1. Land Name (Sheet 5 of 49)
Table 8-1. Land Name (Sheet 6 of 49)
Table 8-1. Land Name (Sheet 7 of 49)
Table 8-1. Land Name (Sheet 8 of 49)
Table 8-1. Land Name (Sheet 9 of 49)
Table 8-1. Land Name (Sheet 10 of 49)
Table 8-1. Land Name (Sheet 11 of 49)
Table 8-1. Land Name (Sheet 12 of 49)
Table 8-1. Land Name (Sheet 13 of 49)
Table 8-1. Land Name (Sheet 14 of 49)
Table 8-1. Land Name (Sheet 15 of 49)
Table 8-1. Land Name (Sheet 16 of 49)
Table 8-1. Land Name (Sheet 17 of 49)
Table 8-1. Land Name (Sheet 18 of 49)
Table 8-1. Land Name (Sheet 19 of 49)
Table 8-1. Land Name (Sheet 20 of 49)
Table 8-1. Land Name (Sheet 21 of 49)
Table 8-1. Land Name (Sheet 22 of 49)
Table 8-1. Land Name (Sheet 23 of 49)
Table 8-1. Land Name (Sheet 24 of 49)
Table 8-1. Land Name (Sheet 25 of 49)
Table 8-1. Land Name (Sheet 26 of 49)
Table 8-1. Land Name (Sheet 27 of 49)
Table 8-1. Land Name (Sheet 28 of 49)
Table 8-1. Land Name (Sheet 29 of 49)
Table 8-1. Land Name (Sheet 30 of 49)
Table 8-1. Land Name (Sheet 31 of 49)
Table 8-1. Land Name (Sheet 32 of 49)
Table 8-1. Land Name (Sheet 33 of 49)
Table 8-1. Land Name (Sheet 34 of 49)
Table 8-1. Land Name (Sheet 35 of 49)
Table 8-1. Land Name (Sheet 36 of 49)
Table 8-1. Land Name (Sheet 37 of 49)
Table 8-1. Land Name (Sheet 38 of 49)
Table 8-1. Land Name (Sheet 39 of 49)
Table 8-1. Land Name (Sheet 40 of 49)
Table 8-1. Land Name (Sheet 41 of 49)
Table 8-1. Land Name (Sheet 42 of 49)
Table 8-1. Land Name (Sheet 43 of 49)
Table 8-1. Land Name (Sheet 44 of 49)
Table 8-1. Land Name (Sheet 45 of 49)
Table 8-1. Land Name (Sheet 46 of 49)
Table 8-1. Land Name (Sheet 47 of 49)
Table 8-1. Land Name (Sheet 48 of 49)
Table 8-1. Land Name (Sheet 49 of 49)
8.2 Listing by Land Number
Table 8-2. Land Number (Sheet 1 of 48)
Table 8-2. Land Number (Sheet 2 of 48)
Table 8-2. Land Number (Sheet 3 of 48)
Table 8-2. Land Number (Sheet 4 of 48)
Table 8-2. Land Number (Sheet 5 of 48)
Table 8-2. Land Number (Sheet 6 of 48)
Table 8-2. Land Number (Sheet 7 of 48)
Table 8-2. Land Number (Sheet 8 of 48)
Table 8-2. Land Number (Sheet 9 of 48)
Table 8-2. Land Number (Sheet 10 of 48)
Table 8-2. Land Number (Sheet 11 of 48)
Table 8-2. Land Nu mber (Sheet 12 of 48)
Table 8-2. Land Number (Sheet 13 of 48)
Table 8-2. Land Number (Sheet 14 of 48)
Table 8-2. Land Number (Sheet 15 of 48)
Table 8-2. Land Nu mber (Sheet 16 of 48)
Table 8-2. Land Number (Sheet 17 of 48)
Table 8-2. Land Number (Sheet 18 of 48)
Table 8-2. Land Number (Sheet 19 of 48)
Table 8-2. Land Number (Sheet 20 o f 48)
Table 8-2. Land Number (Sheet 21 of 48)
Table 8-2. Land Number (Sheet 22 of 48)
Table 8-2. Land Number (Sheet 23 of 48)
Table 8-2. Land Nu mber (Sheet 24 of 48)
Table 8-2. Land Number (Sheet 25 of 48)
Table 8-2. Land Number (Sheet 26 of 48)
Table 8-2. Land Number (Sheet 27 of 48)
Table 8-2. Land Nu mber (Sheet 28 of 48)
Table 8-2. Land Number (Sheet 29 of 48)
Table 8-2. Land Number (Sheet 30 of 48)
Table 8-2. Land Number (Sheet 31 of 48)
Table 8-2. Land Nu mber (Sheet 32 of 4 8)
Table 8-2. Land Number (Sheet 33 of 48)
Table 8-2. Land Number (Sheet 34 of 48)
Table 8-2. Land Number (Sheet 35 of 48)
Table 8-2. Land Nu mber (Sheet 36 of 4 8)
Table 8-2. Land Number (Sheet 37 of 48)
Table 8-2. Land Number (Sheet 38 of 48)
Table 8-2. Land Number (Sheet 39 of 48)
Table 8-2. Land Nu mber (Sheet 40 of 4 8)
Table 8-2. Land Number (Sheet 41 of 48)
Table 8-2. Land Number (Sheet 42 of 48)
Table 8-2. Land Number (Sheet 43 of 48)
Table 8-2. Land Nu mber (Sheet 44 of 4 8)
Table 8-2. Land Number (Sheet 45 of 48)
Table 8-2. Land Number (Sheet 46 of 48)
Table 8-2. Land Number (Sheet 47 of 48)
Table 8-2. Land Nu mber (Sheet 48 of 48)
Page
9
Specifications
9.1 Package Mechanical Drawing
Page
Page
Page
9.2 Processor Component Keep-Out Zones
9.3 Package Loading Specifications
9.4 Package Handling Guidelines
9.5 Package Insertion Specifications
9.6 Processor Mass Specification
9.7 Processor Materials
9.8 Processor Markings
10
10.1 Introduction
10.1.1 Available Boxed Thermal Solution Configurations
10.1.2 Intel Thermal Solution STS200C (Passive/Active Combination Heat Sink Solution)
Page
10.2 Mechanical Specifications
10.2.1 Boxed Processor Heat Sink Dimensions and Baseboard Keepout Zones
Figure 10-4. Boxed Processor Motherboard Keepout Zones (1 of 4)
C
LEGEND, SHEETS 1 & 2 ONLY
ACCESS 8
2X FINGER
Figure 10-5. Boxed Processor Motherboard Keepout Zones (2 of 4)
C
SIDE OF MAINBOARD
C
B
Figure 10-6. Boxed Processor Motherboard Keepout Zones (3 of 4)
LEGEND, SHEET 3 ONLY
SIDE OF MAINBOARD
AS VIEWED FROM SECONDARY
Figure 10-7. Boxed Processor Motherboard Keepout Zones (4 of 4)
SECONDARY SIDE 3D HEIGHT RESTRICTION ZONES
AND LEVER OPENING/CLOSING
PRIMARY SIDE 3D HEIGHT RESTRICTION ZONES AND VOLUMETRIC SWEEPS OF LOADPLATE
Figure 10-8. Boxed Processor Heat Sink Volumetric (1 of 2)
C
AIRFLOW DIRECTION
TOP VIEW
Figure 10-9. Boxed Processor Heat Sink Volumetric (2 of 2)
C
AIRFLOW DIRECTION
[]
Page
Page
10.2.2 Boxed Processor Retention Mechanism and Heat Sink Support (ILM-RS)
10.3 Fan Power Supply [STS200C]
10.3.1 Boxed Processor Cooling Requirements
10.3.1.1 STS200C (Passive / Active Combination Heat Sink Solution)
10.3.1.2 STS200P and STS200PNRW (25.5mm Tall Passive Heat Sink Solution) (Blade + 1U + 2U Rack)
10.4 Boxed Processor Contents
The Boxed Processor and Boxed Thermal Solution contents are outlined below.
Table 10-2. 8 Core / 6 Core Server Thermal Solution Boundary Conditions
Table 10-3. 4 Core Server Thermal Solution Boundary Conditions
