Intel CM8062101038606 Processor Reset, System Service Processor SSP Mode Support, BMC Init Mode

2.5.3.5S-states

The processor PECI client is always guaranteed to be operational in the S0 sleep state.

•The Ping(), GetDIB(), GetTemp(), RdPkgConfig(), WrPkgConfig(), RdPCIConfigLocal() and WrPCIConfigLocal() will be fully operational in S0 and S1. Responses in S3 or deeper states are dependent on POWERGOOD assertion status.

•The RdPCIConfig() and RdIAMSR() responses are guaranteed in S0 only. Behavior in S1 or deeper states is indeterminate.

•PECI behavior is indeterminate in the S3, S4 and S5 states and responses to PECI originator requests when the PECI client is in these states cannot be guaranteed.

2.5.3.6Processor Reset

The processor PECI client is fully reset on all RESET_N assertions. Upon deassertion of RESET_N where power is maintained to the processor (otherwise known as a ‘warm reset’), the following are true:

•The PECI client assumes a bus Idle state.

•The Thermal Filtering Constant is retained.

•PECI SOCKET_ID is retained.

•GetTemp() reading resets to 0x0000.

•Any transaction in progress is aborted by the client (as measured by the client no longer participating in the response).

•The processor client is otherwise reset to a default configuration.

The assertion of the CPU_ONLY_RESET signal does not reset the processor PECI client. As such, it will have no impact on the basic PECI commands, namely the Ping(), GetTemp() and GetDIB(). However, it is likely that other PECI commands that utilize processor resources being reset will receive a ‘resource unavailable’ response till the reset sequence is completed.

2.5.3.7System Service Processor (SSP) Mode Support

Sockets in SSP mode have limited PECI command support. Only the following PECI commands will be supported while in SSP mode. Other PECI commands are not guaranteed to complete in this mode.

•Ping

•RdPCIConfigLocal

•WrPCIConfigLocal (all uncore and IIO CSRs within the processor PCI configuration space will be accessible)

•RdPkgConfig (Index 0 only)

Sockets remain in SSP mode until the "Go" handshake is received. This is applicable to the following SSP modes.

2.5.3.7.1BMC INIT Mode

The BMC INIT boot mode is used to provide a quick and efficient means to transfer responsibility for uncore configuration to a service processor like the BMC. In this mode, the socket performs a minimal amount of internal configuration and then waits for the BMC or service processor to complete the initialization.

72	Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
	Datasheet Volume One