Intel E5-4600, E5-2600 manual Client Management, Power-up Sequencing, WrPCIConfigLocal Capabilities

2.5.2.10.3WrPCIConfigLocal() Capabilities

On the processor PECI clients, the PECI WrPCIConfigLocal() command provides a method for programming certain integrated memory controller and IIO functions as described in Table 2-15. Refer to the Intel® Xeon® Processor E5 Product Family Datasheet Volume Two for more details on specific register definitions. It also enables writing to processor REUT (Robust Electrical Unified Test) registers associated with the Intel QPI, PCIe* and DDR3 functions.

Table 2-15. WrPCIConfigLocal() Memory Controller and IIO Device/Function Support

Bus	Device	Function	Offset Range	Description
0000	0-5	0-7	000-FFFh	Integrated I/O (IIO) Configuration Registers
0001	15	0	104h-127h	Integrated Memory Controller MemHot Registers
0001	15	0	180h-1AFh	Integrated Memory Controller SMBus Registers
0001	15	1	080h-0CFh	Integrated Memory Controller RAS Registers (Scrub/Spare)
0001	16	0, 1, 4, 5	104h-18Bh	Integrated Memory Controller Thermal Control Registers
			1F4h-1FFh
0001	16	2, 3, 6, 7	104h-147h	Integrated Memory Controller Error Registers

2.5.3Client Management

2.5.3.1Power-up Sequencing

The PECI client will not be available when the PWRGOOD signal is de-asserted. Any transactions on the bus during this time will be completely ignored, and the host will read the response from the client as all zeroes. PECI client initialization is completed approximately 100 µS after the PWRGOOD assertion. This is represented by the start of the PECI Client “Data Not Ready” (DNR) phase in Figure 2-49. While in this phase, the PECI client will respond normally to the Ping() and GetDIB() commands and return the highest processor die temperature of 0x0000 to the GetTemp() command. All other commands will get a ‘Response Timeout’ completion in the DNR phase as shown in Table 2-16. All PECI services with the exception of core MSR space accesses become available ~500 µS after RESET_N de-assertion as shown in Figure 2-49. PECI will be fully functional with all services including core accesses being available when the core comes out of reset upon completion of the RESET microcode execution.

In the event of the occurrence of a fatal or catastrophic error, all PECI services with the exception of core MSR space accesses will be available during the DNR phase to facilitate debug through configuration space accesses.

Table 2-16. PECI Client Response During Power-Up (Sheet 1 of 2)

	Command	Response During	Response During
		‘Data Not Ready’	‘Available Except Core Services’
	Ping()	Fully functional	Fully functional
	GetDIB()	Fully functional	Fully functional
	GetTemp()	Client responds with a ‘hot’ reading or 0x0000	Fully functional
	RdPkgConfig()	Client responds with a timeout completion	Fully functional
		code of 0x81
	WrPkgConfig()	Client responds with a timeout completion	Fully functional
		code of 0x81
	RdIAMSR()	Client responds with a timeout completion	Client responds with a timeout
		code of 0x81	completion code of 0x81
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families			69
Datasheet Volume One