Intel CM8062101038606, E5-1600, E5-2600, E5-4600 4.2 Processor Core/Package Power Management

Power Management
90 Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
4.2 Processor Core/Package Power Management
While executing code, Enhanced Intel SpeedStep Technology optimizes the processor’s
frequency and core voltage based on workload. Each frequency and voltage operating
point is defined by ACPI as a P-state. When the processor is not executing code, it is
idle. A low-power idle state is defined by ACPI as a C-state. In general, lower power
C-states have longer entry and exit latencies.
4.2.1 Enhanced Intel SpeedStep® Technology
The following are the key features of Enhanced Intel SpeedStep Technology:
• Multiple frequency and voltage points for optimal performance and power
efficiency. These operating points are known as P-states.
• Frequency selection is software controlled by writing to processor MSRs. The
voltage is optimized based on temperature, leakage, power delivery loadline and
dynamic capacitance.
— If the target frequency is higher than the current frequency, VCC is ramped up
to an optimized voltage. This voltage is signaled by the SVID Bus to the voltage
regulator. Once the voltage is established, the PLL locks on to the target
frequency.
— If the target frequency is lower than the current frequency , the PLL locks to the
target frequency, then transitions to a lower voltage by signaling the target
voltage on the SVID Bus.
— All active processor cores share the same frequency and voltage. In a multi-
core processor, the highest frequency P-state requested amongst all active
cores is selected.
— Software-requested transitions are accepted at any time. The processor has a
new capability from the previous processor generation, it can preempt the
previous transition and complete the new request without waiting for this
request to complete.
• The processor controls voltage ramp rates internally to ensure glitch-free
transitions.
• Because there is low transition latency between P-states, a significant number of
transitions per second are possible.
4.2.2 Low-Power Idle States
When the processor is idle, low-power idle states (C-states) are used to save power.
More power savings actions are taken for numerically higher C-states. However, higher
C-states have longer exit and entry latencies. Resolution of C-states occurs at the
thread, processor core, and processor package level. Thread level C-states are
available if Hyper-Threading Technology is enabled. Entry and exit of the C-States at
the thread and core level are shown in Figure 4-2.