Intel E5-1600, E5-4600 SMBus DC Specifications Sheet 2, Jtag and TAP Signals DC Specifications

Table 7-19. SMBus DC Specifications (Sheet 2 of 2)

Symbol	Parameter	Min	Max	Units	Notes
VIH	Input High Voltage	0.7*VTT		V
VOL	Output Low Voltage		0.2*VTT	V
VOH	Output High Voltage		VTT(max)	V
RON	Buffer On Resistance		14	Ω
IL	Leakage Current	-100	+100	μA
	Signals DDR_SCL_C{01/23}, DDR_SDA_C{01/
	23}
IL	Leakage Current		+900	μA
	Signals PEHPSCL, PEHPSDA

Table 7-20. JTAG and TAP Signals DC Specifications

Symbol	Parameter	Min	Max	Units	Notes
VIL	Input Low Voltage		0.3*VTT	V
VIH	Input High Voltage	0.7*VTT		V
VOL	Output Low Voltage		0.12*VTT	V
	(RTEST = 500 ohm)
VOH	Output High Voltage	0.88*VTT		V
	(RTEST = 500 ohm)
RON	Buffer On Resistance		14	Ω
	Signals BPM_N[7:0], TDO, EAR_N
IIL	Input Leakage Current	-50	+50	μA
	Signals PREQ_N, TCK, TDI, TMS, TRST_N
IIL	Input Leakage Current		+900	μA
	Signals BPM_N[7:0], TDO, EAR_N
	(RTEST = 50 ohm)
IO	Output Current	-1.50	+1.50	mA
	Signal PRDY_N
	(RTEST = 500 ohm)
	Input Edge Rate	0.05		V/ns	1, 2
	Signals: BPM_N[7:0], EAR_N, PREQ_N, TCK,
	TDI, TMS, TRST_N

Note:

1.These signals are measured between VIL and VIH.

2.The signal edge rate must be met or the signal must transition monotonically to the asserted state.

Table 7-21. Serial VID Interface (SVID) DC Specifications (Sheet 1 of 2)

Symbol	Parameter	Min	Typ	Max	Units	Notes
VTT	CPU I/O Voltage	VTT - 3%	1.05	VTT + 3%	V
VIL	Input Low Voltage			0.3*VTT	V	1
	Signals SVIDDATA, SVIDALERT_N
VIH	Input High Voltage	0.7*VTT			V	1
	Signals SVIDDATA, SVIDALERT_N
VOH	Output High Voltage			VTT(max)	V	1
	Signals SVIDCLK, SVIDDATA

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families	179
Datasheet Volume One