Serial VID Interface Svid Signals | Intel CM8062101038606, E5-4600

Signal Descriptions

6.8Serial VID Interface (SVID) Signals

Table 6-13. SVID Signals

SVIDALERT_N	Serial VID alert.

SVIDCLK	Serial VID clock.

SVIDDATA	Serial VID data out.

6.9Processor Asynchronous Sideband and Miscellaneous Signals

Table 6-14. Processor Asynchronous Sideband Signals (Sheet 1 of 3)

	Signal Name	Description

	BIST_ENABLE	BIST Enable Strap. Input which allows the platform to enable or disable built-in self test
		(BIST) on the processor. This signal is pulled up on the die, refer to Table 7-6for details.

	BMCINIT	BMC Initialization Strap. Indicates whether Service Processor Boot Mode should be used.
		Used in combination with FRMAGENT and SOCKET_ID inputs.
		• 0: Service Processor Boot Mode Disabled. Example boot modes: Local PCH (this
		processor hosts a legacy PCH with firmware behind it), Intel QPI Link Boot (for
		processors one hop away from the FW agent), or Intel QPI Link Init (for processors
		more than one hop away from the firmware agent).
		• 1: Service Processor Boot Mode Enabled. In this mode of operation, the processor
		performs the absolute minimum internal configuration and then waits for the Service
		Processor to complete its initialization. The socket boots after receiving a “GO”
		handshake signal via a firmware scratchpad register.
		This signal is pulled down on the die, refer to Table 7-6for details.

	CAT_ERR_N	Indicates that the system has experienced a fatal or catastrophic error and cannot
		continue to operate. The processor will assert CAT_ERR_N for nonrecoverable machine
		check errors and other internal unrecoverable errors. It is expected that every processor
		in the system will wire-OR CAT_ERR_N for all processors. Since this is an I/O land,
		external agents are allowed to assert this land which will cause the processor to take a
		machine check exception. This signal is sampled after PWRGOOD assertion.
		On the processor, CAT_ERR_N is used for signaling the following types of errors:
		• Legacy MCERR’s, CAT_ERR_N is asserted for 16 BCLKs.
		• Legacy IERR’s, CAT_ERR_N remains asserted until warm or cold reset.

	CPU_ONLY_RESET	Resets all the processors on the platform without resetting the DMI2 links.

	ERROR_N[2:0]	Error status signals for integrated I/O (IIO) unit:
		• 0 = Hardware correctable error (no operating system or firmware action necessary)
		• 1 = Non-fatal error (operating system or firmware action required to contain and
		recover)
		• 2 = Fatal error (system reset likely required to recover)

	FRMAGENT	Bootable Firmware Agent Strap. This input configuration strap used in combination with
		SOCKET_ID to determine whether the socket is a legacy socket, bootable firmware agent
		is present, and DMI links are used in PCIe* mode (instead of DMI2 mode).
		The firmware flash ROM is located behind the local PCH attached to the processor via the
		DMI2 interface.This signal is pulled down on the die, refer to Table 7-6for details.

	MEM_HOT_C01_N	Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two
	MEM_HOT_C23_N	modes of operation – input and output mode.
		Input mode is externally asserted and is used to detect external events such as VR_HOT#
		from the memory voltage regulator and causes the processor to throttle the appropriate
		memory channels.
		Output mode is asserted by the processor known as level mode. In level mode, the
		output indicates that a particular branch of memory subsystem is hot.
		MEM_HOT_C01_N is used for memory channels 0 & 1 while MEM_HOT_C23_N is used for
		memory channels 2 & 3.

	PMSYNC	Power Management Sync. A sideband signal to communicate power management status
		from the Platform Controller Hub (PCH) to the processor.

148		Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
		Datasheet Volume One

Image 148

Intel CM8062101038606 manual Serial VID Interface Svid Signals, Processor Asynchronous Sideband and Miscellaneous Signals

Contents

Datasheet Volume One MayPage Contents Package Thermal Specifications Mechanical Specifications 245 10.2.1 Figures Tcase 8-Core 135W Thermal Profile 2U Tables Core 150W Thermal Profile, Workstation Platform SKU Only Fault Resilient Booting Output Tri-State Signals Revision Description Revision Date Number Initial Release March Datasheet Volume One Overview Introduction Processor Feature Details Supported Technologies InterfacesSystem Memory Support PCI Express NTB Intel QuickPath Interconnect Intel QPI Direct Media Interface Gen 2 DMI2Link Power Management Support Platform Environment Control Interface PeciProcessor Package and Core States System States Support Thermal Management Support Package SummaryTerminology Intel QuickPath Interconnect IMC IIOIHS IOV LLC LrdimmNctf Nebs Related Documents TDPTsod Udimm State of Data Referenced Documents Sheet 2 System Memory Technology Support System Memory InterfaceSystem Memory Timing Support PCI Express* Interface PCI Express* Architecture PCI Express* Configuration Mechanism Transaction LayerData Link Layer Physical Layer 1 DMI2 Error Flow DMI2/PCI Express* InterfaceIntel QuickPath Interconnect Processor/PCH Compatibility Assumptions Interfaces Summary of Processor-specific Peci Commands Command Supported on the ProcessorPlatform Environment Control Interface Peci Peci Client Capabilities Client Command Suite Processor Interface Tuning and DiagnosticsThermal Management Platform Manageability GetDIB Minor Revision Supported Command Suite Device InfoRevision Number Minor Revision Number Meaning Client Address Write Length Read Length GetTempTemp70 Temp158 RdPkgConfig Supported ResponsesGetTemp Response Definition Response Meaning WrPkgConfig RdPkgConfig Response Definition WrPkgConfig Response Definition Sheet 1 Electrical error or AW FCS failure WrPkgConfig Response Definition Sheet 2 Package Configuration CapabilitiesDram Thermal and Power Optimization Capabilities Temperature Dram PowerBy power Dram Rank Dram Thermal Estimation Configuration Data Read/Write Limit DataLimit Performance Dram Rank Temperature Write Dimm Temperature ReadChannel & Dimm Index Decoding Index Encoding Physical Channel# Physical DIMM# Dram Channel Temperature Read Dimm Ambient Temperature Write / ReadDIMM# Accumulated Dram Energy Read Dram Power Info ReadAccumulated Dram Energy Data Maximum Time Dram Power Limit Data Write / ReadTypical Value Dram Powerlimit Dram Power Limit Performance Status ReadReserved CPU Thermal and Power Optimization Capabilities CpuidCSR did CSR Mcaerrsrclog Read Mode bit Accumulated Power Limit forVCC Power Read status Read Package Power Modes Package PowerIndicator Read Limits For Package Identifier Read ProcessorType Flag Package Power SKU Unit Read Max Thread Package Power SKU Read Power Control Register Unit CalculationsUnit Field Value Calculation Default Value Wake on Peci Mode Bit Write / Read Package Temperature ReadMaximum Package Power Window Peci Temperature Temperature Target Read Per Core DTS Temperature ReadPackage Thermal Status Read / Clear Thermal Averaging Constant Write / Read Thermally Constrained Time ReadCurrent Limit Read 4 3 2 1 Power Limit for the VCC Power Plane Write / Read Accumulated Energy Status Read Control Time Clamp Power Limit Package Power Limits For Multiple Turbo ModesMode Enable Package Power Limit Performance Status Read Window #2 Mode #2 Enable #2 Efficient Performance Indicator Read Acpi P-T Notify Write & Read Read Mode bit 11 = ‘0’ Core ID Bit Read Mode bit 11 = ‘1’Caching Agent TOR Read Thermal Margin Read RdIAMSR Processor ID Enumeration 42. Processor ID Construction Example 10. RdIAMSR Response Definition 11. RdIAMSR Services Summary Sheet 1RdIAMSR Capabilities 11. RdIAMSR Services Summary Sheet 2 Or ID Address Meaning Sor ID Byte Dword RdPCIConfig 44. PCI Configuration Address RdPCIConfigLocal 12. RdPCIConfig Response DefinitionTimely fashion. Retry is appropriate Appropriate PCI Configuration Address 13. RdPCIConfigLocal Response Definition Sheet 10x05 0x02,0x03,0x05 0xe1 Definition WrPCIConfigLocal 13. RdPCIConfigLocal Response Definition Sheet 2 14. WrPCIConfigLocal Response Definition Cmd Code0xe5 Completion Power-up Sequencing WrPCIConfigLocal Capabilities16. Peci Client Response During Power-Up Sheet 1 Client Management Device Discovery 16. Peci Client Response During Power-Up Sheet 2Client Addressing 18. Power Impact of Peci Commands vs. C-states Command Power ImpactStates 17. Socket ID Strapping System Service Processor SSP Mode Support Processor ResetBMC Init Mode Originator Retry and Timeout Policy Processor Error HandlingLink Init Mode Multi-Domain Commands 20. Multi-Domain Command Code ReferenceEnumerating Peci Client Capabilities 19. Domain ID Definition Client Responses Abort FCSCompletion Codes 21. Completion Code Pass/Fail Mask DTS Temperature Data Originator ResponsesFormat Interpretation Temperature Filtering 24. Error Codes and DescriptionsError Code Description Reserved Values Datasheet Volume One Intel Virtualization Technology Intel VT Intel VT-x Objectives Intel VT-d Features Supported Intel VT-x FeaturesIntel VT-d Objectives Intel Virtualization Technology Processor Extensions Security TechnologiesIntel Trusted Execution Technology Intel Trusted Execution Technology Server Extensions Intel Advanced Encryption Standard Instructions Intel AES-NI Execute Disable Bit Intel Turbo Boost Operating Frequency Enhanced Intel SpeedStep Technology Intel Intelligent Power TechnologyIntel Advanced Vector Extensions Intel AVX Intel Dynamic Power Technology Intel DPT Technologies Acpi States Supported System StatesSystem States Package C-State Support Sheet 1 System Memory Power States Sheet 1 Integrated Memory Controller StatesPackage C-State Support Sheet 2 Core C-State Support Intel QuickPath Interconnect States 4 DMI2/PCI Express Link States6 G, S, and C State Combinations Low-Power Idle States Processor Core/Package Power ManagementEnhanced Intel SpeedStep Technology Requesting Low-Power Idle States Idle Power Management Breakdown of the Processor Cores Core C-states Core C0 StateCore C1/C1E State PLVLx to Mwait Conversion Core C3 State Core C6 StateCore C7 State State Auto-Demotion Package C-States Coordination of Core Power States at the Package Level Package C0Package C1/C1E Package C-State Core Package C3 State Package C2 StatePackage C6 State System Memory Power Management Package C-State Power Specifications10. Package C-State Power Specifications TDP SKUs C1E W C3 W C6 W Core / 6-Core CKE Power-Down Self RefreshSelf Refresh Entry Self Refresh Exit Dram I/O Power Management DMI2/PCI Express* Power ManagementDLL and PLL Shutdown 100 Package Thermal Specifications Thermal Specifications Tcase and DTS Based Thermal Specifications Temperaturetarget MSR Processor Thermal Profiles 3.1 8-Core 150W Thermal SpecificationsProcessor SKU Summary Table Thermal Management Specifications Power W Maximum T Case C Maximum Dtsc Core 150W Thermal Profile, Workstation Platform SKU Only Tcase 8-Core 135W Thermal Specifications 2U 3.2 8-Core 135W Thermal Specifications3, 4 Power W Maximum Tcase C Maximum DTS C Core 135W Thermal Profile U Sheet 1 Power W Maximum T Case C Maximum DTS C 3.3 8/6-Core 130W Thermal SpecificationsCore 135W Thermal Profile U Sheet 2 Tcase 8/6-Core 130W Thermal Profile 1U Power W Maximum Tcase C Maximum DTS C Core 6-Core 130W Thermal Profile U Sheet 1 3.4 6-Core 130W 1S WS Thermal Specifications Tcase 6-Core 130W 1S WS Thermal SpecificationsPower W Maximum T Case C Maximum DTS C Core 6-Core 130W Thermal Profile U Sheet 2 DTS 6-Core 130W 1S WS Thermal Profile Core 130W 1S WS Thermal Profile Table Sheet 1 10. Tcase 8-Core 115W Thermal Specifications 1U 3.5 8-Core 115W Thermal SpecificationsCore 130W 1S WS Thermal Profile Table Sheet 2 10. Tcase 8-Core 115W Thermal Profile 1U 3.6 8/6-Core 95W Thermal Specifications 11 -Core 115W Thermal Profile U 12. Tcase 8/6-Core 95W Thermal Profile 1U 14. DTS 6-Core 95W Thermal Profile 1U 13 /6-Core 95W Thermal Profile U Sheet 1 14. Tcase 8-Core 70W Thermal Specifications 1U 3.7 8-Core 70W Thermal Specifications13 /6-Core 95W Thermal Profile U Sheet 2 16. DTS 8-Core 70W Thermal Profile 1U 15 -Core 70W Thermal Profile U 3.8 6-Core 60W Thermal Specifications 16. Tcase 6-Core 60W Thermal Specifications 1U 18. DTS 6-Core 60W Thermal Profile 1U 17 -Core 60W Thermal Profile U 3.9 4-Core 130W Thermal Specifications 18. Tcase 4-Core 130W Thermal Specifications 2U 20. DTS 4-Core 130W Thermal Profile 2U 19 -Core 130W Thermal Profile U Sheet 1 3.10 4-Core 130W 1S WS Thermal Specifications 19 -Core 130W Thermal Profile U Sheet 2 21. Tcase 4-Core 130W 1S WS Thermal Profile 22. Tcase 4-Core 95W Thermal Specifications 1U 3.11 4-Core 95W Thermal Specifications21 -Core 130W 1S WS Thermal Profile Table 23. Tcase 4-Core 95W Thermal Profile 1U 24. Tcase 4/2-Core 80W Thermal Specifications 1U 3.12 4/2-Core 80W Thermal Specifications23 -Core 95W Thermal Profile U 25. Tcase 4/2-Core 80W Thermal Profile 1U Maximum Tcase Maximum DTS C Power W Core 25 /2-Core 80W Thermal Profile U Sheet 1 4.1 8-Core LV95W Thermal Specifications Maximum T Case Maximum DTS C Power W CoreEmbedded Server Processor Thermal Profiles 25 /2-Core 80W Thermal Profile U Sheet 2 28. Tcase 8-Core LV95W Thermal Profile, Embedded Server SKU 29. DTS 8-Core LV95W Thermal Profile, Embedded Server SKU 4.2 8-Core LV70W Thermal Specifications 30. Tcase 8-Core LV70W Thermal Profile, Embedded Server SKU 31. DTS 8-Core LV70W Thermal Profile, Embedded Server SKU 32. Case Temperature Tcase Measurement Location Thermal Metrology Processor Temperature Processor Core Thermal FeaturesAdaptive Thermal Monitor Frequency/SVID Control 33. Frequency and Voltage Ordering Prochotn Signal On-Demand ModeClock Modulation Integrated Memory Controller IMC Thermal Features Thermtripn SignalDram Throttling Options Hybrid Closed Loop Thermal Throttling CLTTHybrid MEMHOTC01N and MEMHOTC23N SignalIntegrated Dual SMBus Master Controllers for SMI Signal Name Description System Memory Interface SignalsMemory Channel DDR0, DDR1, DDR2, DDR3 PCI Express* Based Interface Signals PCI Express* Port 1 SignalsPCI Express* Port 2 Signals Sheet 1 Memory Channel Miscellaneous PCI Express* Port 3 Signals PCI Express* Port 2 Signals Sheet 2PCI Express* Miscellaneous Signals Sheet 1 DMI2/PCI Express* Port 0 Signals Intel QuickPath Interconnect Signals System Reference Clock Signals Peci SignalJtag and TAP Signals Serial VID Interface Svid Signals Processor Asynchronous Sideband and Miscellaneous Signals13. Svid Signals 14. Processor Asynchronous Sideband Signals Sheet 1 14. Processor Asynchronous Sideband Signals Sheet 2 Processor Power and Ground Supplies 14. Processor Asynchronous Sideband Signals Sheet 315. Miscellaneous Signals 16. Power and Ground Signals Sheet 1 16. Power and Ground Signals Sheet 2 152 Processor Signaling System Memory Interface Signal GroupsPCI Express* Signals 3 DMI2/PCI Express* Signals System Reference Clocks BCLK0/1DP, BCLK0/ 1DN Platform Environmental Control Interface PeciInput Device Hysteresis Jtag and Test Access Port TAP Signals Processor Sideband SignalsPower, Ground and Sense Signals PLL Power Supply Power and Ground Lands Power Number Comments Ground LandsDecoupling Guidelines Voltage Identification VID Svid Commands SetVID Fast CommandSetVID Slow Command SetVID-Decay Command Svid Power State Functions SetPS VR Power-State Transitions Svid Voltage Rail Addressing Svid Address UsagePWM Address HEX Processor 159 Signal Group Summary Reserved or Unused SignalsSignal Description Buffer Types Sheet 1 Signal Description Signal Description Buffer Types Sheet 2 Signal Groups Sheet 1 Signal Groups Sheet 2 Signal Groups Sheet 3 Serial VID Interface Svid SignalsProcessor Asynchronous Sideband Signals Miscellaneous Signals Power-On Configuration POC Options Signals with On-Die TerminationPower-On Configuration Option Lands Signal Name Pull Up /Pull Rail Value Units Down Fault Resilient Booting FRB Fault Resilient Booting Output Tri-State SignalsOutput Tri-State Signal Groups Signals Mixing Processors Symbol Parameter Min Max Unit Flexible Motherboard Guidelines FMBAbsolute Maximum and Minimum Ratings Processor Absolute Minimum and Maximum Ratings Storage Conditions Specifications 10. Storage Condition Ratings DC Specifications Voltage and Current Specifications 11. Voltage SpecificationSymbol Parameter Voltage Min Typ Max Unit Plane VCC VID 12. Processor Current Specifications Parameter Symbol Processor TDP / Core CountMax a Definition Core/6-core 13 /6 Core Processor VCC Static and Transient Tolerance CC a ICC a VID 3,4,5,6 100 105 110 115 120 125 130 135 140 145 150 174 VCC Overshoot Specifications 15. VCC Overshoot Specifications Sheet 1Symbol Parameter Min Max Units Die Voltage Validation 15. VCC Overshoot Specifications Sheet 2 Signal DC Specifications16. DDR3 and DDR3L Signal DC Specifications Sheet 1 16. DDR3 and DDR3L Signal DC Specifications Sheet 2 Reference Clock SignalCommand Signals Control Signals 17. Peci DC Specifications 18. System Reference Clock BCLK0/1 DC Specifications19. SMBus DC Specifications Sheet 1 Symbol Definition and Conditions Min Max Units 19. SMBus DC Specifications Sheet 2 20. Jtag and TAP Signals DC Specifications21. Serial VID Interface Svid DC Specifications Sheet 1 Symbol Parameter Min Typ Max Units 21. Serial VID Interface Svid DC Specifications Sheet 2 22. Processor Asynchronous Sideband DC SpecificationsCMOS1.05v Signals Open Drain Cmos Odcmos Signals PCI Express* DC Specifications 3.2 DMI2/PCI Express* DC SpecificationsIntel QuickPath Interconnect DC Specifications Reset and Miscellaneous Signal DC Specifications Stable VRB-DifferentialVcross MAX = 550mV Vcross MIN = 250mV 1 DDR3 Signal Quality Specifications Signal Quality2 I/O Signal Quality Specifications Intel QuickPath Interconnect Signal Quality Specifications Input Reference Clock Signal Quality Specifications24. Processor I/O Overshoot/Undershoot Specifications Overshoot/Undershoot Tolerance Overshoot/Undershoot Pulse Duration Reading Overshoot/Undershoot Specification TablesActivity Factor 11. Maximum Acceptable Overshoot/Undershoot Waveform Listing by Land Name Land Name Sheet 1Land Name Sheet 2 Land Name Land No Buffer Type Direction Land Name Sheet 3 Land Name Sheet 4 Land Name Sheet 5 Land Name Sheet 6 Land Name Sheet 7 Land Name Sheet 8 Land Name Sheet 9 Land Name Sheet 10 Land Name Sheet 11 Land Name Sheet 12 Land Name Sheet 13 Land Name Sheet 14 Land Name Sheet 15 Land Name Sheet 16 Land Name Sheet 17 Land Name Sheet 18 Land Name Sheet 19 Land Name Sheet 20 Land Name Sheet 21 Land Name Sheet 22 Land Name Sheet 23 Land Name Sheet 24 Land Name Sheet 25 Land Name Sheet 26 Land Name Sheet 27 Land Name Sheet 28 Land Name Sheet 29 Land Name Sheet 30 Land Name Sheet 31 Land Name Sheet 32 Land Name Sheet 33 Land Name Sheet 34VCCD01 VCCD23 Land Name Sheet 35 Land Name Sheet 36 Land Name Sheet 37 Land Name Sheet 38 Land Name Sheet 39 Land Name Sheet 40 Land Name Sheet 41 Land Name Sheet 42 Land Name Sheet 43 Land Name Sheet 44 Land Name Sheet 45 Land Name Sheet 46 Land Name Sheet 47 Land Name Sheet 48Vtta Vttd Land Name Sheet 49 Listing by Land Number Land Number Sheet 1Land Number Sheet 2 Land No Land Name Buffer Type Direction Land Number Sheet 3 Land Number Sheet 4 Land Number Sheet 5 Land Number Sheet 6 Land Number Sheet 7 Land Number Sheet 8 Land Number Sheet 9 Land Number Sheet 10 Land Number Sheet 11 Land Number Sheet 12 Land Number Sheet 13 Land Number Sheet 14 Land Number Sheet 15 Land Number Sheet 16 Land Number Sheet 17 Land Number Sheet 18 Land Number Sheet 19 Land Number Sheet 20 Land Number Sheet 21 Land Number Sheet 22 Land Number Sheet 23 Land Number Sheet 24 Land Number Sheet 25 Land Number Sheet 26 Land Number Sheet 27 Land Number Sheet 28 Land Number Sheet 29 Land Number Sheet 30 Land Number Sheet 31 Land Number Sheet 32 Land Number Sheet 33 Land Number Sheet 34 Land Number Sheet 35 Land Number Sheet 36 Land Number Sheet 37 Land Number Sheet 38 Land Number Sheet 39 Land Number Sheet 40 Land Number Sheet 41 Land Number Sheet 42 Land Number Sheet 43 Land Number Sheet 44 Land Number Sheet 45 Land Number Sheet 46 Land Number Sheet 47 Land Number Sheet 48 236 Processor Package Assembly Sketch Package Mechanical Drawing 238 Processor Package Drawing Sheet 1 Processor Package Drawing Sheet 2 Package Loading Specifications Package Insertion SpecificationsProcessor Component Keep-Out Zones Package Handling Guidelines Processor Mass Specification Processor MaterialsProcessor Markings Processor Materials Boxed Processor Specifications Available Boxed Thermal Solution Configurations 244 Mechanical Specifications STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks Motherboard Keepout Zones 1 246 Boxed Processor Specifications Motherboard Keepout Zones 2 Boxed Processor Motherboard Keepout Zones 3 248 Motherboard Keepout Zones 4 TOP Surface of Motherboard Boxed Processor Heat Sink Volumetric 1 250 Heat Sink Volumetric 2 SpecificationsProcessor Boxed Processor 10.4-Pin Fan Cable Connector For Active Heat Sink 11 -Pin Base Baseboard Fan Header For Active Heat Sink Fan Power Supply STS200C 21,000 25,000 28,000 Boxed Processor Cooling Requirements Boxed Processor Contents Boxed Processor 258