Figure 2-42. Processor ID Construction Example

 

 

 

 

 

Cores 0,1.2...7

 

 

 

 

 

 

 

 

 

 

C7

C6

 

C5

C4

 

 

C3

C2

 

C1

 

C0

 

 

T1

T0

T1

T0

T1

T0

T1

T0

T1

T0

T1

T0

T1

T0

T1

T0

 

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

0

Processor

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ID

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(0..15)

 

 

 

 

 

Thread (0,1) Mask for Core4

 

 

 

 

 

 

 

 

Figure 2-43. RdIAMSR()

 

 

 

 

 

 

 

 

 

 

 

 

Note: The 2-byte MSR Address field and read data field defined in Figure 2-43are sent in standard PECI ordering with LSB first and MSB last.

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

61

Datasheet Volume One

 

Page 61
Image 61
Intel E5-4600, CM8062101038606, E5-2600, E5-1600 manual Processor ID Construction Example