Intel E5-4600, E5-2600 DDR3 and DDR3L Signal DC Specifications Sheet 2, Reference Clock Signal

Table 7-16. DDR3 and DDR3L Signal DC Specifications (Sheet 2 of 2)

Symbol Parameter Min Typ Max Units Notes1

VOL	Output Low Voltage		(VCCD/ 2)* (RON /(RON+RVTT_TERM))		V	2, 7
VOH	Output High Voltage		VCCD- ((VCCD / 2)* (RON/		V	2, 5, 7
			(RON+RVTT_TERM))
Reference Clock Signal
RON	DDR3 Clock Buffer On	21		31	Ω	6
	Resistance
Command Signals
RON	DDR3 Command Buffer On	16		24	Ω	6
	Resistance
RON	DDR3 Reset Buffer On	25		75	Ω	6
	Resistance
VOL_CMOS1.5v	Output Low Voltage, Signals			0.2*VCCD	V	1,2
	DDR_RESET_ C{01/23}_N
VOH_CMOS1.5v	Output High Voltage, Signals	0.9*VCCD			V	1,2
	DDR_RESET_ C{01/23}_N
IIL_CMOS1.5v	Input Leakage Current	-100		+100	μA	1,2
Control Signals
RON	DDR3 Control Buffer On	21		31	Ω	6
	Resistance
DDR01_RCOMP[0	COMP Resistance	128.7	130	131.3	Ω	9,12
]
DDR01_RCOMP[1	COMP Resistance	25.839	26.1	26.361	Ω	9,12
]
DDR01_RCOMP[2	COMP Resistance	198	200	202	Ω	9,12
]
DDR23_RCOMP[0	COMP Resistance	128.7	130	131.3	Ω	9,12
]
DDR23_RCOMP[1	COMP Resistance	25.839	26.1	26.361	Ω	9,12
]
DDR23_RCOMP[2	COMP Resistance	198	200	202	Ω	9,12
]
DDR3 Miscellaneous Signals
VIL	Input Low Voltage			0.55*VCC	V	2, 3,
	DRAM_PWR_OK_C{01/23}			D - 0.2		11, 13
VIH	Input High Voltage	0.55*VCC			V	2, 4, 5,
	DRAM_PWR_OK_C{01/23}	D + 0.3				11, 13

Notes:

1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.

2.The voltage rail VCCD which will be set to 1.50 V or 1.35 V nominal depending on the voltage of all DIMMs connected to the processor.

3.VIL is the maximum voltage level at a receiving agent that will be interpreted as a logical low value.

4.VIH is the minimum voltage level at a receiving agent that will be interpreted as a logical high value.

5.VIH and VOH may experience excursions above VCCD. However, input signal drivers must comply with the signal quality specifications. Refer to Section 7.9.

6.This is the pull down driver resistance. Refer to processor signal integrity models for I/V characteristics. Reset drive does not have a termination.

7.RVTT_TERM is the termination on the DIMM and not controlled by the processor. Please refer to the applicable DIMM datasheet.

8.The minimum and maximum values for these signals are programmable by BIOS to one of the pairs.

9.COMP resistance must be provided on the system board with 1% resistors. See the applicable platform design guide for implementation details. DDR01_RCOMP[2:0] and DDR23_RCOMP[2:0] resistors are terminated to VSS.

10.Input leakage current is specified for all DDR3 signals.

11.DRAM_PWR_OK_C{01/23} must have a maximum of 30 ns rise or fall time over VCCD * 0.55 +300 mV and -200 mV and the edge must be monotonic.

12.The DDR01/23_RCOMP error tolerance is ± 15% from the compensated value.

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families	177
Datasheet Volume One