PCI Express* Interface, PCI Express* Architecture | Intel E5-2600

Interfaces

2.2PCI Express* Interface

This section describes the PCI Express* 3.0 interface capabilities of the processor. See the PCI Express* Base Specification for details of PCI Express* 3.0.

2.2.1PCI Express* Architecture

Compatibility with the PCI addressing model is maintained to ensure that all existing applications and drivers operate unchanged. The PCI Express* configuration uses standard mechanisms as defined in the PCI Plug-and-Play specification.

The PCI Express* architecture is specified in three layers: Transaction Layer, Data Link Layer, and Physical Layer. The partitioning in the component is not necessarily along these same boundaries. Refer to Figure 2-1for the PCI Express* Layering Diagram.

Figure 2-1. PCI Express* Layering Diagram

Transaction

Data Link

Physical

Logical Sub-Block

Electrical Sub-Block

RX TX

Transaction

Data Link

Physical

Logical Sub-Block

Electrical Sub-Block

RX TX

PCI Express* uses packets to communicate information between components. Packets are formed in the Transaction and Data Link Layers to carry the information from the transmitting component to the receiving component. As the transmitted packets flow through the other layers, they are extended with additional information necessary to handle packets at those layers. At the receiving side, the reverse process occurs and packets get transformed from their Physical Layer representation to the Data Link Layer representation and finally (for Transaction Layer Packets) to the form that can be processed by the Transaction Layer of the receiving device.

26	Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
	Datasheet Volume One

Image 26

Intel E5-2600, CM8062101038606, E5-4600, E5-1600 manual PCI Express* Interface, PCI Express* Architecture

Contents

Datasheet Volume One MayPage Contents Package Thermal Specifications Mechanical Specifications 245 10.2.1 Figures Tcase 8-Core 135W Thermal Profile 2U Tables Core 150W Thermal Profile, Workstation Platform SKU Only Fault Resilient Booting Output Tri-State Signals Revision Description Revision Date Number Initial Release March Datasheet Volume One Overview Introduction Processor Feature Details System Memory Support InterfacesSupported Technologies PCI Express NTB Link Direct Media Interface Gen 2 DMI2Intel QuickPath Interconnect Intel QPI Processor Package and Core States Power Management SupportPlatform Environment Control Interface Peci System States Support Terminology Thermal Management SupportPackage Summary Intel QuickPath Interconnect IHS IMCIIO IOV Nctf LLCLrdimm Nebs Tsod Related DocumentsTDP Udimm State of Data Referenced Documents Sheet 2 System Memory Timing Support System Memory InterfaceSystem Memory Technology Support PCI Express* Interface PCI Express* Architecture Data Link Layer PCI Express* Configuration MechanismTransaction Layer Physical Layer Intel QuickPath Interconnect 1 DMI2 Error FlowDMI2/PCI Express* Interface Processor/PCH Compatibility Assumptions Interfaces Platform Environment Control Interface Peci Summary of Processor-specific Peci CommandsCommand Supported on the Processor Peci Client Capabilities Thermal Management Client Command SuiteProcessor Interface Tuning and Diagnostics Platform Manageability GetDIB Revision Number Minor Revision Supported Command SuiteDevice Info Minor Revision Number Meaning Temp70 Temp158 GetTempClient Address Write Length Read Length GetTemp Response Definition RdPkgConfigSupported Responses Response Meaning WrPkgConfig RdPkgConfig Response Definition WrPkgConfig Response Definition Sheet 1 Electrical error or AW FCS failure Dram Thermal and Power Optimization Capabilities Package Configuration CapabilitiesWrPkgConfig Response Definition Sheet 2 By power TemperatureDram Power Dram Rank Limit Dram Thermal Estimation Configuration Data Read/WriteLimit Data Performance Channel & Dimm Index Decoding Dram Rank Temperature WriteDimm Temperature Read Index Encoding Physical Channel# Physical DIMM# DIMM# Dimm Ambient Temperature Write / ReadDram Channel Temperature Read Accumulated Dram Energy Data Dram Power Info ReadAccumulated Dram Energy Read Typical Value Dram Power Limit Data Write / ReadMaximum Time Reserved Dram Power Limit Performance Status ReadDram Powerlimit CSR did CPU Thermal and Power Optimization CapabilitiesCpuid CSR Mcaerrsrclog VCC Power Read Mode bit AccumulatedPower Limit for Read status Indicator Read Read Package PowerModes Package Power Limits For Type Package Identifier ReadProcessor Flag Package Power SKU Unit Read Max Thread Unit Field Value Calculation Default Value Power Control Register Unit CalculationsPackage Power SKU Read Maximum Package Power Window Wake on Peci Mode Bit Write / ReadPackage Temperature Read Peci Temperature Package Thermal Status Read / Clear Per Core DTS Temperature ReadTemperature Target Read Current Limit Read Thermal Averaging Constant Write / ReadThermally Constrained Time Read 4 3 2 1 Power Limit for the VCC Power Plane Write / Read Accumulated Energy Status Read Mode Enable Package Power Limits For Multiple Turbo ModesControl Time Clamp Power Limit Package Power Limit Performance Status Read Window #2 Mode #2 Enable #2 Efficient Performance Indicator Read Acpi P-T Notify Write & Read Caching Agent TOR Read Read Mode bit 11 = ‘0’Core ID Bit Read Mode bit 11 = ‘1’ Thermal Margin Read RdIAMSR Processor ID Enumeration 42. Processor ID Construction Example RdIAMSR Capabilities 11. RdIAMSR Services Summary Sheet 110. RdIAMSR Response Definition 11. RdIAMSR Services Summary Sheet 2 Or ID Address Meaning Sor ID Byte Dword RdPCIConfig 44. PCI Configuration Address Timely fashion. Retry is appropriate RdPCIConfigLocal12. RdPCIConfig Response Definition Appropriate 0x05 0x02,0x03,0x05 0xe1 Definition 13. RdPCIConfigLocal Response Definition Sheet 1PCI Configuration Address WrPCIConfigLocal 13. RdPCIConfigLocal Response Definition Sheet 2 0xe5 14. WrPCIConfigLocal Response DefinitionCmd Code Completion 16. Peci Client Response During Power-Up Sheet 1 Power-up SequencingWrPCIConfigLocal Capabilities Client Management Client Addressing 16. Peci Client Response During Power-Up Sheet 2Device Discovery States 18. Power Impact of Peci Commands vs. C-statesCommand Power Impact 17. Socket ID Strapping BMC Init Mode Processor ResetSystem Service Processor SSP Mode Support Link Init Mode Processor Error HandlingOriginator Retry and Timeout Policy Enumerating Peci Client Capabilities Multi-Domain Commands20. Multi-Domain Command Code Reference 19. Domain ID Definition Completion Codes Client ResponsesAbort FCS 21. Completion Code Pass/Fail Mask Format DTS Temperature DataOriginator Responses Interpretation Error Code Description Temperature Filtering24. Error Codes and Descriptions Reserved Values Datasheet Volume One Intel Virtualization Technology Intel VT Intel VT-x Objectives Intel VT-d Objectives Intel VT-x FeaturesIntel VT-d Features Supported Intel Trusted Execution Technology Security TechnologiesIntel Virtualization Technology Processor Extensions Intel Trusted Execution Technology Server Extensions Intel Advanced Encryption Standard Instructions Intel AES-NI Execute Disable Bit Intel Turbo Boost Operating Frequency Intel Advanced Vector Extensions Intel AVX Intel Intelligent Power TechnologyEnhanced Intel SpeedStep Technology Intel Dynamic Power Technology Intel DPT Technologies System States Acpi States SupportedSystem States Package C-State Support Sheet 1 Package C-State Support Sheet 2 System Memory Power States Sheet 1Integrated Memory Controller States Core C-State Support 6 G, S, and C State Combinations 4 DMI2/PCI Express Link StatesIntel QuickPath Interconnect States Enhanced Intel SpeedStep Technology Processor Core/Package Power ManagementLow-Power Idle States Requesting Low-Power Idle States Idle Power Management Breakdown of the Processor Cores Core C1/C1E State Core C-statesCore C0 State PLVLx to Mwait Conversion Core C7 State Core C3 StateCore C6 State State Auto-Demotion Package C-States Package C1/C1E Coordination of Core Power States at the Package LevelPackage C0 Package C-State Core Package C6 State Package C2 StatePackage C3 State 10. Package C-State Power Specifications System Memory Power ManagementPackage C-State Power Specifications TDP SKUs C1E W C3 W C6 W Core / 6-Core Self Refresh Entry CKE Power-DownSelf Refresh Self Refresh Exit DLL and PLL Shutdown DMI2/PCI Express* Power ManagementDram I/O Power Management 100 Package Thermal Specifications Thermal Specifications Tcase and DTS Based Thermal Specifications Temperaturetarget MSR Processor SKU Summary Table 3.1 8-Core 150W Thermal SpecificationsProcessor Thermal Profiles Thermal Management Specifications Power W Maximum T Case C Maximum Dtsc Core 150W Thermal Profile, Workstation Platform SKU Only 3, 4 3.2 8-Core 135W Thermal SpecificationsTcase 8-Core 135W Thermal Specifications 2U Power W Maximum Tcase C Maximum DTS C Core 135W Thermal Profile U Sheet 1 Core 135W Thermal Profile U Sheet 2 3.3 8/6-Core 130W Thermal SpecificationsPower W Maximum T Case C Maximum DTS C Tcase 8/6-Core 130W Thermal Profile 1U Power W Maximum Tcase C Maximum DTS C Core 6-Core 130W Thermal Profile U Sheet 1 Power W Maximum T Case C Maximum DTS C Core 3.4 6-Core 130W 1S WS Thermal SpecificationsTcase 6-Core 130W 1S WS Thermal Specifications 6-Core 130W Thermal Profile U Sheet 2 DTS 6-Core 130W 1S WS Thermal Profile Core 130W 1S WS Thermal Profile Table Sheet 1 Core 130W 1S WS Thermal Profile Table Sheet 2 3.5 8-Core 115W Thermal Specifications10. Tcase 8-Core 115W Thermal Specifications 1U 10. Tcase 8-Core 115W Thermal Profile 1U 3.6 8/6-Core 95W Thermal Specifications 11 -Core 115W Thermal Profile U 12. Tcase 8/6-Core 95W Thermal Profile 1U 14. DTS 6-Core 95W Thermal Profile 1U 13 /6-Core 95W Thermal Profile U Sheet 1 13 /6-Core 95W Thermal Profile U Sheet 2 3.7 8-Core 70W Thermal Specifications14. Tcase 8-Core 70W Thermal Specifications 1U 16. DTS 8-Core 70W Thermal Profile 1U 15 -Core 70W Thermal Profile U 3.8 6-Core 60W Thermal Specifications 16. Tcase 6-Core 60W Thermal Specifications 1U 18. DTS 6-Core 60W Thermal Profile 1U 17 -Core 60W Thermal Profile U 3.9 4-Core 130W Thermal Specifications 18. Tcase 4-Core 130W Thermal Specifications 2U 20. DTS 4-Core 130W Thermal Profile 2U 19 -Core 130W Thermal Profile U Sheet 1 3.10 4-Core 130W 1S WS Thermal Specifications 19 -Core 130W Thermal Profile U Sheet 2 21. Tcase 4-Core 130W 1S WS Thermal Profile 21 -Core 130W 1S WS Thermal Profile Table 3.11 4-Core 95W Thermal Specifications22. Tcase 4-Core 95W Thermal Specifications 1U 23. Tcase 4-Core 95W Thermal Profile 1U 23 -Core 95W Thermal Profile U 3.12 4/2-Core 80W Thermal Specifications24. Tcase 4/2-Core 80W Thermal Specifications 1U 25. Tcase 4/2-Core 80W Thermal Profile 1U Maximum Tcase Maximum DTS C Power W Core 25 /2-Core 80W Thermal Profile U Sheet 1 Embedded Server Processor Thermal Profiles 4.1 8-Core LV95W Thermal SpecificationsMaximum T Case Maximum DTS C Power W Core 25 /2-Core 80W Thermal Profile U Sheet 2 28. Tcase 8-Core LV95W Thermal Profile, Embedded Server SKU 29. DTS 8-Core LV95W Thermal Profile, Embedded Server SKU 4.2 8-Core LV70W Thermal Specifications 30. Tcase 8-Core LV70W Thermal Profile, Embedded Server SKU 31. DTS 8-Core LV70W Thermal Profile, Embedded Server SKU 32. Case Temperature Tcase Measurement Location Thermal Metrology Adaptive Thermal Monitor Processor Core Thermal FeaturesProcessor Temperature Frequency/SVID Control 33. Frequency and Voltage Ordering Clock Modulation On-Demand ModeProchotn Signal Dram Throttling Options Thermtripn SignalIntegrated Memory Controller IMC Thermal Features Integrated Dual SMBus Master Controllers for SMI MEMHOTC01N and MEMHOTC23N SignalHybrid Closed Loop Thermal Throttling CLTTHybrid Memory Channel DDR0, DDR1, DDR2, DDR3 System Memory Interface SignalsSignal Name Description PCI Express* Port 2 Signals Sheet 1 PCI Express* Based Interface SignalsPCI Express* Port 1 Signals Memory Channel Miscellaneous PCI Express* Miscellaneous Signals Sheet 1 PCI Express* Port 2 Signals Sheet 2PCI Express* Port 3 Signals DMI2/PCI Express* Port 0 Signals Intel QuickPath Interconnect Signals Jtag and TAP Signals Peci SignalSystem Reference Clock Signals 13. Svid Signals Serial VID Interface Svid SignalsProcessor Asynchronous Sideband and Miscellaneous Signals 14. Processor Asynchronous Sideband Signals Sheet 1 14. Processor Asynchronous Sideband Signals Sheet 2 15. Miscellaneous Signals Processor Power and Ground Supplies14. Processor Asynchronous Sideband Signals Sheet 3 16. Power and Ground Signals Sheet 1 16. Power and Ground Signals Sheet 2 152 PCI Express* Signals Processor SignalingSystem Memory Interface Signal Groups 3 DMI2/PCI Express* Signals Input Device Hysteresis Platform Environmental Control Interface PeciSystem Reference Clocks BCLK0/1DP, BCLK0/ 1DN Power, Ground and Sense Signals Jtag and Test Access Port TAP SignalsProcessor Sideband Signals PLL Power Supply Decoupling Guidelines Power and Ground LandsPower Number Comments Ground Lands Voltage Identification VID SetVID Slow Command Svid CommandsSetVID Fast Command SetVID-Decay Command Svid Power State Functions SetPS VR Power-State Transitions PWM Address HEX Processor Svid Voltage Rail AddressingSvid Address Usage 159 Signal Description Buffer Types Sheet 1 Signal Group SummaryReserved or Unused Signals Signal Description Signal Description Buffer Types Sheet 2 Signal Groups Sheet 1 Signal Groups Sheet 2 Processor Asynchronous Sideband Signals Signal Groups Sheet 3Serial VID Interface Svid Signals Miscellaneous Signals Power-On Configuration Option Lands Power-On Configuration POC OptionsSignals with On-Die Termination Signal Name Pull Up /Pull Rail Value Units Down Output Tri-State Signal Groups Signals Fault Resilient Booting FRBFault Resilient Booting Output Tri-State Signals Mixing Processors Absolute Maximum and Minimum Ratings Symbol Parameter Min Max UnitFlexible Motherboard Guidelines FMB Processor Absolute Minimum and Maximum Ratings Storage Conditions Specifications 10. Storage Condition Ratings DC Specifications Symbol Parameter Voltage Min Typ Max Unit Plane Voltage and Current Specifications11. Voltage Specification VCC VID Max a Definition 12. Processor Current SpecificationsParameter Symbol Processor TDP / Core Count Core/6-core 13 /6 Core Processor VCC Static and Transient Tolerance CC a ICC a VID 3,4,5,6 100 105 110 115 120 125 130 135 140 145 150 174 Symbol Parameter Min Max Units VCC Overshoot Specifications15. VCC Overshoot Specifications Sheet 1 Die Voltage Validation 16. DDR3 and DDR3L Signal DC Specifications Sheet 1 Signal DC Specifications15. VCC Overshoot Specifications Sheet 2 Command Signals 16. DDR3 and DDR3L Signal DC Specifications Sheet 2Reference Clock Signal Control Signals 19. SMBus DC Specifications Sheet 1 17. Peci DC Specifications18. System Reference Clock BCLK0/1 DC Specifications Symbol Definition and Conditions Min Max Units 21. Serial VID Interface Svid DC Specifications Sheet 1 19. SMBus DC Specifications Sheet 220. Jtag and TAP Signals DC Specifications Symbol Parameter Min Typ Max Units CMOS1.05v Signals 21. Serial VID Interface Svid DC Specifications Sheet 222. Processor Asynchronous Sideband DC Specifications Open Drain Cmos Odcmos Signals Intel QuickPath Interconnect DC Specifications PCI Express* DC Specifications3.2 DMI2/PCI Express* DC Specifications Reset and Miscellaneous Signal DC Specifications Vcross MAX = 550mV StableVRB-Differential Vcross MIN = 250mV 2 I/O Signal Quality Specifications Signal Quality1 DDR3 Signal Quality Specifications 24. Processor I/O Overshoot/Undershoot Specifications Intel QuickPath Interconnect Signal Quality SpecificationsInput Reference Clock Signal Quality Specifications Overshoot/Undershoot Tolerance Activity Factor Reading Overshoot/Undershoot Specification TablesOvershoot/Undershoot Pulse Duration 11. Maximum Acceptable Overshoot/Undershoot Waveform Land Name Sheet 2 Listing by Land NameLand Name Sheet 1 Land Name Land No Buffer Type Direction Land Name Sheet 3 Land Name Sheet 4 Land Name Sheet 5 Land Name Sheet 6 Land Name Sheet 7 Land Name Sheet 8 Land Name Sheet 9 Land Name Sheet 10 Land Name Sheet 11 Land Name Sheet 12 Land Name Sheet 13 Land Name Sheet 14 Land Name Sheet 15 Land Name Sheet 16 Land Name Sheet 17 Land Name Sheet 18 Land Name Sheet 19 Land Name Sheet 20 Land Name Sheet 21 Land Name Sheet 22 Land Name Sheet 23 Land Name Sheet 24 Land Name Sheet 25 Land Name Sheet 26 Land Name Sheet 27 Land Name Sheet 28 Land Name Sheet 29 Land Name Sheet 30 Land Name Sheet 31 Land Name Sheet 32 VCCD01 Land Name Sheet 33Land Name Sheet 34 VCCD23 Land Name Sheet 35 Land Name Sheet 36 Land Name Sheet 37 Land Name Sheet 38 Land Name Sheet 39 Land Name Sheet 40 Land Name Sheet 41 Land Name Sheet 42 Land Name Sheet 43 Land Name Sheet 44 Land Name Sheet 45 Land Name Sheet 46 Vtta Land Name Sheet 47Land Name Sheet 48 Vttd Land Name Sheet 49 Land Number Sheet 2 Listing by Land NumberLand Number Sheet 1 Land No Land Name Buffer Type Direction Land Number Sheet 3 Land Number Sheet 4 Land Number Sheet 5 Land Number Sheet 6 Land Number Sheet 7 Land Number Sheet 8 Land Number Sheet 9 Land Number Sheet 10 Land Number Sheet 11 Land Number Sheet 12 Land Number Sheet 13 Land Number Sheet 14 Land Number Sheet 15 Land Number Sheet 16 Land Number Sheet 17 Land Number Sheet 18 Land Number Sheet 19 Land Number Sheet 20 Land Number Sheet 21 Land Number Sheet 22 Land Number Sheet 23 Land Number Sheet 24 Land Number Sheet 25 Land Number Sheet 26 Land Number Sheet 27 Land Number Sheet 28 Land Number Sheet 29 Land Number Sheet 30 Land Number Sheet 31 Land Number Sheet 32 Land Number Sheet 33 Land Number Sheet 34 Land Number Sheet 35 Land Number Sheet 36 Land Number Sheet 37 Land Number Sheet 38 Land Number Sheet 39 Land Number Sheet 40 Land Number Sheet 41 Land Number Sheet 42 Land Number Sheet 43 Land Number Sheet 44 Land Number Sheet 45 Land Number Sheet 46 Land Number Sheet 47 Land Number Sheet 48 236 Processor Package Assembly Sketch Package Mechanical Drawing 238 Processor Package Drawing Sheet 1 Processor Package Drawing Sheet 2 Processor Component Keep-Out Zones Package Loading SpecificationsPackage Insertion Specifications Package Handling Guidelines Processor Markings Processor Mass SpecificationProcessor Materials Processor Materials Boxed Processor Specifications Available Boxed Thermal Solution Configurations 244 Mechanical Specifications STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks Motherboard Keepout Zones 1 246 Boxed Processor Specifications Motherboard Keepout Zones 2 Boxed Processor Motherboard Keepout Zones 3 248 Motherboard Keepout Zones 4 TOP Surface of Motherboard Boxed Processor Heat Sink Volumetric 1 250 Processor Heat Sink Volumetric 2Specifications Boxed Processor 10.4-Pin Fan Cable Connector For Active Heat Sink 11 -Pin Base Baseboard Fan Header For Active Heat Sink Fan Power Supply STS200C 21,000 25,000 28,000 Boxed Processor Cooling Requirements Boxed Processor Contents Boxed Processor 258