Intel E5-1600 Accumulated Dram Energy Read, Dram Power Info Read, Accumulated Dram Energy Data

Figure 2-16. Processor DRAM Channel Temperature

31	24	23	16	15	8	7	0
Channel 3			Channel 2		Channel 1		Channel 0
Maximum			Maximum		Maximum		Maximum
Temperature			Temperature		Temperature		Temperature
(in Degrees C)			(in Degrees C)		(in Degrees C)		(in Degrees C)

Channel Temperature Data

2.5.2.6.7Accumulated DRAM Energy Read

This feature allows the PECI host to read the DRAM energy consumed by all the DIMMs within all the channels or all the DIMMs within just a specified channel. The parameter field is used to specify the channel index. Units used are defined as per the Package Power SKU Unit read described in Section 2.5.2.6.11. This information is tracked by a 32-bit counter that wraps around. The channel index in Figure 2-17is specified as per the index encoding described in Table 2-7. A channel index of 0x00FF is used to specify the “all channels” case. While Intel requires reading the accumulated energy data at least once every 16 seconds to ensure functional correctness, a more realistic polling rate recommendation is once every 100 mS for better accuracy. This feature assumes a 200W memory capacity. In general, as the power capability decreases, so will the minimum polling rate requirement.

When determining energy changes by subtracting energy values between successive reads, Intel advocates using the 2’s complement method to account for counter wrap- arounds. Alternatively, adding all ‘F’s (‘0xFFFFFFFF’) to a negative result from the subtraction will accomplish the same goal.

Figure 2-17. Accumulated DRAM Energy Data

31			0
	Accumulated DRAM Energy
	Accumulated DRAM Energy Data
15	3	2	0
	Reserved		Channel Index
	Parameter format

2.5.2.6.8DRAM Power Info Read

This read returns the minimum, typical and maximum DRAM power settings and the maximum time window over which the power can be sustained for the entire DRAM domain and is inclusive of all the DIMMs within all the memory channels. Any power values specified by the power limiting entity that is outside of the range specified through these settings cannot be guaranteed. Since this data is 64 bits wide, PECI facilitates access to this register by allowing two requests to read the lower 32 bits and upper 32 bits separately as shown in Table 2-6. Power and time units for this read are defined as per the Package Power SKU Unit settings described in Section 2.5.2.6.11.

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families	43
Datasheet Volume One