2.5.2.6.11CPU Thermal and Power Optimization Capabilities

Table 2-8provides a summary of the processor power and thermal optimization capabilities that can be accessed over PECI.

Note: The Index values referenced in Table 2-8are in decimal format.

Table 2-8also provides information on alternate inband mechanisms to access similar or equivalent information for register reads and writes where applicable. The user should consult the appropriate Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 or Intel® Xeon® Processor E5 Product Family Datasheet Volume Two for exact details on MSR or CSR register content.

Table 2-8. RdPkgConfig() & WrPkgConfig() CPU Thermal and Power Optimization Services Summary (Sheet 1 of 3)

 

Index

Parameter

RdPkgConfig()

WrPkgConfig()

 

Alternate Inband

Service

Value

Value

Data (dword)

Description

Data (dword)

MSR or CSR Access

 

(decimal)

(word)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Returns processor-

 

 

 

 

CPUID

 

specific information

Execute CPUID instruction to get

 

 

0x0000

 

including CPU family,

 

 

 

Information

 

model and stepping

processor signature

 

 

 

 

 

information.

 

 

 

 

 

 

 

 

 

 

 

 

 

Used to ensure

 

 

 

0x0001

Platform ID

 

microcode update

MSR 17h: IA32_PLATFORM_ID

 

 

 

compatibility with

 

 

 

 

 

 

 

 

 

 

 

processor.

 

 

 

 

 

 

 

 

 

 

 

 

 

Returns the Device

 

Package

 

0x0002

PCU Device ID

 

ID information for

CSR: DID

00

 

the processor Power

Identifier Read

 

 

 

Control Unit.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Returns the

MSR: RESOLVED_CORES_MASK

 

 

0x0003

Max Thread ID

 

maximum ‘Thread

 

 

 

ID’ value supported

CSR: RESOLVED_CORES_MASK

 

 

 

 

 

 

 

 

 

 

by the processor.

 

 

 

 

 

 

 

 

 

 

 

 

 

Returns processor

 

 

 

0x0004

CPU Microcode

 

microcode and PCU

MSR 8Bh: IA32_BIOS_SIGN_ID

 

 

 

Update Revision

 

firmware revision

 

 

 

 

 

 

information.

 

 

 

 

 

 

 

 

 

 

0x0005

MCA Error

 

Returns the MCA

CSR: MCA_ERR_SRC_LOG

 

 

Source Log

 

Error Source Log

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Read units for power,

MSR 606h:

Package Power

30

0x0000

Time, Energy

N/A

energy and time

PACKAGE_POWER_SKU_UNIT

SKU Unit Read

and Power Units

used in power

CSR:

 

 

 

 

 

control registers.

PACKAGE_POWER_SKU_UNIT

 

 

 

 

 

 

 

 

 

 

 

 

Returns Thermal

MSR 614h:

Package Power

 

 

Package Power

N/A

Design Power and

28

0x0000

minimum package

PACKAGE_POWER_SKU

SKU Read

SKU[31:0]

 

 

 

 

power values for the

CSR: PACKAGE_POWER_SKU

 

 

 

 

 

 

 

 

 

 

processor SKU.

 

 

 

 

 

 

 

 

 

 

 

 

 

Returns the

 

 

 

 

 

 

maximum package

MSR 614h:

Package Power

 

 

Package Power

 

power value for the

29

0x0000

N/A

processor SKU and

PACKAGE_POWER_SKU

SKU Read

SKU[64:32]

 

 

 

the maximum time

CSR: PACKAGE_POWER_SKU

 

 

 

 

 

 

 

 

 

 

interval for which it

 

 

 

 

 

 

can be sustained.

 

 

 

 

 

 

 

 

“Wake on PECI”

 

0x0001 - Set

 

 

Enables package

 

05

N/A

“Wake on PECI”

pop-up to C2 to

N/A

0x0000 -

Mode Bit Write /

mode bit

service PECI

Read

 

Reset

 

PCIConfig() accesses

 

 

 

 

 

 

 

 

 

 

if appropriate.

 

 

 

 

 

 

 

 

46

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

 

Datasheet Volume One

Page 46
Image 46
Intel E5-2600, CM8062101038606 manual CPU Thermal and Power Optimization Capabilities, Cpuid, CSR did, CSR Mcaerrsrclog, Csr