Device Info, Revision Number, 5 4 3 2 1 | Intel E5-4600, E5-2600

2.5.2.2.2Device Info

The Device Info byte gives details regarding the PECI client configuration. At a minimum, all clients supporting GetDIB will return the number of domains inside the package via this field. With any client, at least one domain (Domain 0) must exist. Therefore, the Number of Domains reported is defined as the number of domains in addition to Domain 0. For example, if bit 2 of the Device Info byte returns a ‘1’, that would indicate that the PECI client supports two domains.

Figure 2-6. Device Info Field Definition

Byte# 5

7 6 5 4 3 2 1 0

Reserved

#of Domains Reserved

2.5.2.2.3Revision Number

All clients that support the GetDIB command also support Revision Number reporting. The revision number may be used by a host or originator to manage different command suites or response codes from the client. Revision Number is always reported in the second byte of the GetDIB() response. The ‘Major Revision’ number in Figure 2-7always maps to the revision number of the PECI specification that the PECI client processor is designed to. The ‘Minor Revision’ number value depends on the exact command suite supported by the PECI client as defined in Table 2-2.

Figure 2-7. Revision Number Definition

						Byte# 6
		7		4			3		0


		Major Revision#
		Major Revision#
		Minor Revision#
		Minor Revision#

Table 2-2. Minor Revision Number Meaning

	Minor Revision		Supported Command Suite

	0			Ping(), GetDIB(), GetTemp()

	1	Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig()

	2	Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR()

	3	Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(),
		RdPCIConfigLocal(), WrPCIConfigLocal()

	4	Ping(), GetDIB(), GetTemp(), WrPkgConfig(), RdPkgConfig(), RdIAMSR(),
		RdPCIConfigLocal(), WrPCIConfigLocal(), RdPCIConfig()

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families	33
Datasheet Volume One

Image 33

Intel E5-4600, E5-2600 Device Info, Minor Revision Number Meaning, 5 4 3 2 1, Minor Revision Supported Command Suite

Contents

May Datasheet Volume OnePage Contents Package Thermal Specifications Mechanical Specifications 245 10.2.1 Figures Tcase 8-Core 135W Thermal Profile 2U Tables Core 150W Thermal Profile, Workstation Platform SKU Only Fault Resilient Booting Output Tri-State Signals Initial Release March Revision Description Revision Date Number Datasheet Volume One Introduction Overview Processor Feature Details Interfaces Supported TechnologiesSystem Memory Support PCI Express NTB Direct Media Interface Gen 2 DMI2 Intel QuickPath Interconnect Intel QPILink Platform Environment Control Interface Peci Power Management SupportProcessor Package and Core States System States Support Package Summary Thermal Management SupportTerminology Intel QuickPath Interconnect IIO IMCIHS IOV Lrdimm LLCNctf Nebs TDP Related DocumentsTsod Udimm Referenced Documents Sheet 2 State of Data System Memory Interface System Memory Technology SupportSystem Memory Timing Support PCI Express* Architecture PCI Express* Interface Transaction Layer PCI Express* Configuration MechanismData Link Layer Physical Layer DMI2/PCI Express* Interface 1 DMI2 Error FlowIntel QuickPath Interconnect Processor/PCH Compatibility Assumptions Interfaces Command Supported on the Processor Summary of Processor-specific Peci CommandsPlatform Environment Control Interface Peci Peci Client Capabilities Processor Interface Tuning and Diagnostics Client Command SuiteThermal Management Platform Manageability GetDIB Device Info Minor Revision Supported Command SuiteRevision Number Minor Revision Number Meaning GetTemp Client Address Write Length Read LengthTemp70 Temp158 Supported Responses RdPkgConfigGetTemp Response Definition Response Meaning RdPkgConfig Response Definition WrPkgConfig Electrical error or AW FCS failure WrPkgConfig Response Definition Sheet 1 Package Configuration Capabilities WrPkgConfig Response Definition Sheet 2Dram Thermal and Power Optimization Capabilities Dram Power TemperatureBy power Dram Rank Limit Data Dram Thermal Estimation Configuration Data Read/WriteLimit Performance Dimm Temperature Read Dram Rank Temperature WriteChannel & Dimm Index Decoding Index Encoding Physical Channel# Physical DIMM# Dimm Ambient Temperature Write / Read Dram Channel Temperature ReadDIMM# Dram Power Info Read Accumulated Dram Energy ReadAccumulated Dram Energy Data Dram Power Limit Data Write / Read Maximum TimeTypical Value Dram Power Limit Performance Status Read Dram PowerlimitReserved Cpuid CPU Thermal and Power Optimization CapabilitiesCSR did CSR Mcaerrsrclog Power Limit for Read Mode bit AccumulatedVCC Power Read status Modes Package Power Read Package PowerIndicator Read Limits For Processor Package Identifier ReadType Flag Max Thread Package Power SKU Unit Read Power Control Register Unit Calculations Package Power SKU ReadUnit Field Value Calculation Default Value Package Temperature Read Wake on Peci Mode Bit Write / ReadMaximum Package Power Window Peci Temperature Per Core DTS Temperature Read Temperature Target ReadPackage Thermal Status Read / Clear Thermally Constrained Time Read Thermal Averaging Constant Write / ReadCurrent Limit Read 4 3 2 1 Accumulated Energy Status Read Power Limit for the VCC Power Plane Write / Read Package Power Limits For Multiple Turbo Modes Control Time Clamp Power LimitMode Enable Window #2 Mode #2 Enable #2 Package Power Limit Performance Status Read Acpi P-T Notify Write & Read Efficient Performance Indicator Read Core ID Bit Read Mode bit 11 = ‘1’ Read Mode bit 11 = ‘0’Caching Agent TOR Read Thermal Margin Read Processor ID Enumeration RdIAMSR 42. Processor ID Construction Example 11. RdIAMSR Services Summary Sheet 1 10. RdIAMSR Response DefinitionRdIAMSR Capabilities Or ID Address Meaning Sor ID Byte Dword 11. RdIAMSR Services Summary Sheet 2 44. PCI Configuration Address RdPCIConfig 12. RdPCIConfig Response Definition RdPCIConfigLocalTimely fashion. Retry is appropriate Appropriate 13. RdPCIConfigLocal Response Definition Sheet 1 PCI Configuration Address0x05 0x02,0x03,0x05 0xe1 Definition 13. RdPCIConfigLocal Response Definition Sheet 2 WrPCIConfigLocal Cmd Code 14. WrPCIConfigLocal Response Definition0xe5 Completion WrPCIConfigLocal Capabilities Power-up Sequencing16. Peci Client Response During Power-Up Sheet 1 Client Management 16. Peci Client Response During Power-Up Sheet 2 Device DiscoveryClient Addressing Command Power Impact 18. Power Impact of Peci Commands vs. C-statesStates 17. Socket ID Strapping Processor Reset System Service Processor SSP Mode SupportBMC Init Mode Processor Error Handling Originator Retry and Timeout PolicyLink Init Mode 20. Multi-Domain Command Code Reference Multi-Domain CommandsEnumerating Peci Client Capabilities 19. Domain ID Definition Abort FCS Client ResponsesCompletion Codes 21. Completion Code Pass/Fail Mask Originator Responses DTS Temperature DataFormat Interpretation 24. Error Codes and Descriptions Temperature FilteringError Code Description Reserved Values Datasheet Volume One Intel VT-x Objectives Intel Virtualization Technology Intel VT Intel VT-x Features Intel VT-d Features SupportedIntel VT-d Objectives Security Technologies Intel Virtualization Technology Processor ExtensionsIntel Trusted Execution Technology Intel Advanced Encryption Standard Instructions Intel AES-NI Intel Trusted Execution Technology Server Extensions Intel Turbo Boost Operating Frequency Execute Disable Bit Intel Intelligent Power Technology Enhanced Intel SpeedStep TechnologyIntel Advanced Vector Extensions Intel AVX Intel Dynamic Power Technology Intel DPT Technologies System States Acpi States SupportedSystem States Package C-State Support Sheet 1 Integrated Memory Controller States System Memory Power States Sheet 1Package C-State Support Sheet 2 Core C-State Support 4 DMI2/PCI Express Link States Intel QuickPath Interconnect States6 G, S, and C State Combinations Processor Core/Package Power Management Low-Power Idle StatesEnhanced Intel SpeedStep Technology Idle Power Management Breakdown of the Processor Cores Requesting Low-Power Idle States Core C0 State Core C-statesCore C1/C1E State PLVLx to Mwait Conversion Core C6 State Core C3 StateCore C7 State State Auto-Demotion Package C-States Package C0 Coordination of Core Power States at the Package LevelPackage C1/C1E Package C-State Core Package C2 State Package C3 StatePackage C6 State Package C-State Power Specifications System Memory Power Management10. Package C-State Power Specifications TDP SKUs C1E W C3 W C6 W Core / 6-Core Self Refresh CKE Power-DownSelf Refresh Entry Self Refresh Exit DMI2/PCI Express* Power Management Dram I/O Power ManagementDLL and PLL Shutdown 100 Thermal Specifications Package Thermal Specifications Tcase and DTS Based Thermal Specifications Temperaturetarget MSR 3.1 8-Core 150W Thermal Specifications Processor Thermal ProfilesProcessor SKU Summary Table Thermal Management Specifications Core 150W Thermal Profile, Workstation Platform SKU Only Power W Maximum T Case C Maximum Dtsc 3.2 8-Core 135W Thermal Specifications Tcase 8-Core 135W Thermal Specifications 2U3, 4 Core 135W Thermal Profile U Sheet 1 Power W Maximum Tcase C Maximum DTS C 3.3 8/6-Core 130W Thermal Specifications Power W Maximum T Case C Maximum DTS CCore 135W Thermal Profile U Sheet 2 Tcase 8/6-Core 130W Thermal Profile 1U 6-Core 130W Thermal Profile U Sheet 1 Power W Maximum Tcase C Maximum DTS C Core Tcase 6-Core 130W 1S WS Thermal Specifications 3.4 6-Core 130W 1S WS Thermal SpecificationsPower W Maximum T Case C Maximum DTS C Core 6-Core 130W Thermal Profile U Sheet 2 Core 130W 1S WS Thermal Profile Table Sheet 1 DTS 6-Core 130W 1S WS Thermal Profile 3.5 8-Core 115W Thermal Specifications 10. Tcase 8-Core 115W Thermal Specifications 1UCore 130W 1S WS Thermal Profile Table Sheet 2 10. Tcase 8-Core 115W Thermal Profile 1U 11 -Core 115W Thermal Profile U 3.6 8/6-Core 95W Thermal Specifications 12. Tcase 8/6-Core 95W Thermal Profile 1U 13 /6-Core 95W Thermal Profile U Sheet 1 14. DTS 6-Core 95W Thermal Profile 1U 3.7 8-Core 70W Thermal Specifications 14. Tcase 8-Core 70W Thermal Specifications 1U13 /6-Core 95W Thermal Profile U Sheet 2 15 -Core 70W Thermal Profile U 16. DTS 8-Core 70W Thermal Profile 1U 16. Tcase 6-Core 60W Thermal Specifications 1U 3.8 6-Core 60W Thermal Specifications 17 -Core 60W Thermal Profile U 18. DTS 6-Core 60W Thermal Profile 1U 18. Tcase 4-Core 130W Thermal Specifications 2U 3.9 4-Core 130W Thermal Specifications 19 -Core 130W Thermal Profile U Sheet 1 20. DTS 4-Core 130W Thermal Profile 2U 19 -Core 130W Thermal Profile U Sheet 2 3.10 4-Core 130W 1S WS Thermal Specifications 21. Tcase 4-Core 130W 1S WS Thermal Profile 3.11 4-Core 95W Thermal Specifications 22. Tcase 4-Core 95W Thermal Specifications 1U21 -Core 130W 1S WS Thermal Profile Table 23. Tcase 4-Core 95W Thermal Profile 1U 3.12 4/2-Core 80W Thermal Specifications 24. Tcase 4/2-Core 80W Thermal Specifications 1U23 -Core 95W Thermal Profile U 25. Tcase 4/2-Core 80W Thermal Profile 1U 25 /2-Core 80W Thermal Profile U Sheet 1 Maximum Tcase Maximum DTS C Power W Core Maximum T Case Maximum DTS C Power W Core 4.1 8-Core LV95W Thermal SpecificationsEmbedded Server Processor Thermal Profiles 25 /2-Core 80W Thermal Profile U Sheet 2 28. Tcase 8-Core LV95W Thermal Profile, Embedded Server SKU 29. DTS 8-Core LV95W Thermal Profile, Embedded Server SKU 30. Tcase 8-Core LV70W Thermal Profile, Embedded Server SKU 4.2 8-Core LV70W Thermal Specifications 31. DTS 8-Core LV70W Thermal Profile, Embedded Server SKU Thermal Metrology 32. Case Temperature Tcase Measurement Location Processor Core Thermal Features Processor TemperatureAdaptive Thermal Monitor 33. Frequency and Voltage Ordering Frequency/SVID Control On-Demand Mode Prochotn SignalClock Modulation Thermtripn Signal Integrated Memory Controller IMC Thermal FeaturesDram Throttling Options MEMHOTC01N and MEMHOTC23N Signal Hybrid Closed Loop Thermal Throttling CLTTHybridIntegrated Dual SMBus Master Controllers for SMI System Memory Interface Signals Signal Name DescriptionMemory Channel DDR0, DDR1, DDR2, DDR3 PCI Express* Port 1 Signals PCI Express* Based Interface SignalsPCI Express* Port 2 Signals Sheet 1 Memory Channel Miscellaneous PCI Express* Port 2 Signals Sheet 2 PCI Express* Port 3 SignalsPCI Express* Miscellaneous Signals Sheet 1 Intel QuickPath Interconnect Signals DMI2/PCI Express* Port 0 Signals Peci Signal System Reference Clock SignalsJtag and TAP Signals Processor Asynchronous Sideband and Miscellaneous Signals Serial VID Interface Svid Signals13. Svid Signals 14. Processor Asynchronous Sideband Signals Sheet 1 14. Processor Asynchronous Sideband Signals Sheet 2 14. Processor Asynchronous Sideband Signals Sheet 3 Processor Power and Ground Supplies15. Miscellaneous Signals 16. Power and Ground Signals Sheet 1 16. Power and Ground Signals Sheet 2 152 System Memory Interface Signal Groups Processor SignalingPCI Express* Signals 3 DMI2/PCI Express* Signals Platform Environmental Control Interface Peci System Reference Clocks BCLK0/1DP, BCLK0/ 1DNInput Device Hysteresis Processor Sideband Signals Jtag and Test Access Port TAP SignalsPower, Ground and Sense Signals PLL Power Supply Power Number Comments Ground Lands Power and Ground LandsDecoupling Guidelines Voltage Identification VID SetVID Fast Command Svid CommandsSetVID Slow Command SetVID-Decay Command VR Power-State Transitions Svid Power State Functions SetPS Svid Address Usage Svid Voltage Rail AddressingPWM Address HEX Processor 159 Reserved or Unused Signals Signal Group SummarySignal Description Buffer Types Sheet 1 Signal Description Signal Groups Sheet 1 Signal Description Buffer Types Sheet 2 Signal Groups Sheet 2 Serial VID Interface Svid Signals Signal Groups Sheet 3Processor Asynchronous Sideband Signals Miscellaneous Signals Signals with On-Die Termination Power-On Configuration POC OptionsPower-On Configuration Option Lands Signal Name Pull Up /Pull Rail Value Units Down Fault Resilient Booting Output Tri-State Signals Fault Resilient Booting FRBOutput Tri-State Signal Groups Signals Mixing Processors Flexible Motherboard Guidelines FMB Symbol Parameter Min Max UnitAbsolute Maximum and Minimum Ratings Processor Absolute Minimum and Maximum Ratings 10. Storage Condition Ratings Storage Conditions Specifications DC Specifications 11. Voltage Specification Voltage and Current SpecificationsSymbol Parameter Voltage Min Typ Max Unit Plane VCC VID Parameter Symbol Processor TDP / Core Count 12. Processor Current SpecificationsMax a Definition Core/6-core CC a 13 /6 Core Processor VCC Static and Transient Tolerance ICC a VID 3,4,5,6 100 105 110 115 120 125 130 135 140 145 150 174 15. VCC Overshoot Specifications Sheet 1 VCC Overshoot SpecificationsSymbol Parameter Min Max Units Die Voltage Validation Signal DC Specifications 15. VCC Overshoot Specifications Sheet 216. DDR3 and DDR3L Signal DC Specifications Sheet 1 Reference Clock Signal 16. DDR3 and DDR3L Signal DC Specifications Sheet 2Command Signals Control Signals 18. System Reference Clock BCLK0/1 DC Specifications 17. Peci DC Specifications19. SMBus DC Specifications Sheet 1 Symbol Definition and Conditions Min Max Units 20. Jtag and TAP Signals DC Specifications 19. SMBus DC Specifications Sheet 221. Serial VID Interface Svid DC Specifications Sheet 1 Symbol Parameter Min Typ Max Units 22. Processor Asynchronous Sideband DC Specifications 21. Serial VID Interface Svid DC Specifications Sheet 2CMOS1.05v Signals Open Drain Cmos Odcmos Signals 3.2 DMI2/PCI Express* DC Specifications PCI Express* DC SpecificationsIntel QuickPath Interconnect DC Specifications Reset and Miscellaneous Signal DC Specifications VRB-Differential StableVcross MAX = 550mV Vcross MIN = 250mV Signal Quality 1 DDR3 Signal Quality Specifications2 I/O Signal Quality Specifications Input Reference Clock Signal Quality Specifications Intel QuickPath Interconnect Signal Quality Specifications24. Processor I/O Overshoot/Undershoot Specifications Overshoot/Undershoot Tolerance Reading Overshoot/Undershoot Specification Tables Overshoot/Undershoot Pulse DurationActivity Factor 11. Maximum Acceptable Overshoot/Undershoot Waveform Land Name Sheet 1 Listing by Land NameLand Name Sheet 2 Land Name Land No Buffer Type Direction Land Name Sheet 4 Land Name Sheet 3 Land Name Sheet 6 Land Name Sheet 5 Land Name Sheet 8 Land Name Sheet 7 Land Name Sheet 10 Land Name Sheet 9 Land Name Sheet 12 Land Name Sheet 11 Land Name Sheet 14 Land Name Sheet 13 Land Name Sheet 16 Land Name Sheet 15 Land Name Sheet 18 Land Name Sheet 17 Land Name Sheet 20 Land Name Sheet 19 Land Name Sheet 22 Land Name Sheet 21 Land Name Sheet 24 Land Name Sheet 23 Land Name Sheet 26 Land Name Sheet 25 Land Name Sheet 28 Land Name Sheet 27 Land Name Sheet 30 Land Name Sheet 29 Land Name Sheet 32 Land Name Sheet 31 Land Name Sheet 34 Land Name Sheet 33VCCD01 VCCD23 Land Name Sheet 36 Land Name Sheet 35 Land Name Sheet 38 Land Name Sheet 37 Land Name Sheet 40 Land Name Sheet 39 Land Name Sheet 42 Land Name Sheet 41 Land Name Sheet 44 Land Name Sheet 43 Land Name Sheet 46 Land Name Sheet 45 Land Name Sheet 48 Land Name Sheet 47Vtta Vttd Land Name Sheet 49 Land Number Sheet 1 Listing by Land NumberLand Number Sheet 2 Land No Land Name Buffer Type Direction Land Number Sheet 4 Land Number Sheet 3 Land Number Sheet 6 Land Number Sheet 5 Land Number Sheet 8 Land Number Sheet 7 Land Number Sheet 10 Land Number Sheet 9 Land Number Sheet 12 Land Number Sheet 11 Land Number Sheet 14 Land Number Sheet 13 Land Number Sheet 16 Land Number Sheet 15 Land Number Sheet 18 Land Number Sheet 17 Land Number Sheet 20 Land Number Sheet 19 Land Number Sheet 22 Land Number Sheet 21 Land Number Sheet 24 Land Number Sheet 23 Land Number Sheet 26 Land Number Sheet 25 Land Number Sheet 28 Land Number Sheet 27 Land Number Sheet 30 Land Number Sheet 29 Land Number Sheet 32 Land Number Sheet 31 Land Number Sheet 34 Land Number Sheet 33 Land Number Sheet 36 Land Number Sheet 35 Land Number Sheet 38 Land Number Sheet 37 Land Number Sheet 40 Land Number Sheet 39 Land Number Sheet 42 Land Number Sheet 41 Land Number Sheet 44 Land Number Sheet 43 Land Number Sheet 46 Land Number Sheet 45 Land Number Sheet 48 Land Number Sheet 47 236 Package Mechanical Drawing Processor Package Assembly Sketch 238 Processor Package Drawing Sheet 1 Processor Package Drawing Sheet 2 Package Insertion Specifications Package Loading SpecificationsProcessor Component Keep-Out Zones Package Handling Guidelines Processor Materials Processor Mass SpecificationProcessor Markings Processor Materials Available Boxed Thermal Solution Configurations Boxed Processor Specifications 244 STS200P and STS200PNRW 25.5 mm Tall Passive Heat Sinks Mechanical Specifications 246 Motherboard Keepout Zones 1 Motherboard Keepout Zones 2 Boxed Processor Specifications 248 Boxed Processor Motherboard Keepout Zones 3 TOP Surface of Motherboard Motherboard Keepout Zones 4 250 Boxed Processor Heat Sink Volumetric 1 Specifications Heat Sink Volumetric 2Processor Boxed Processor 10.4-Pin Fan Cable Connector For Active Heat Sink 11 -Pin Base Baseboard Fan Header For Active Heat Sink 21,000 25,000 28,000 Fan Power Supply STS200C Boxed Processor Cooling Requirements Boxed Processor Contents Boxed Processor 258