Intel CM8062101038606, E5-4600 Dram Thermal Estimation Configuration Data Read/Write, Limit Data

Models: E5-2600 E5-4600 E5-1600 CM8062101038606

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Table 2-6. RdPkgConfig() & WrPkgConfig() DRAM Thermal and Power Optimization Services Summary (Sheet 2 of 2)

 

Index

Parameter

RdPkgConfig()

WrPkgConfig()

 

Alternate Inband

Service

Value

Value

Data

Data

Description

MSR or CSR

 

(decimal)

(word)

(dword)

(dword)

 

Access

 

 

 

 

 

 

 

DRAM Power

 

 

 

 

 

MSR 618h:

Limit Data

 

 

 

DRAM Plane

Write DRAM

DRAM_POWER_LIMIT

Write / Read

34

0x0000

N/A

CSR:

Power Limit Data

Power Limit Data

 

 

 

 

DRAM_PLANE_POWER_LIM

 

 

 

 

 

 

IT

 

 

 

 

 

 

 

DRAM Power

 

 

 

 

 

MSR 618h:

Limit Data

 

 

DRAM Plane Power

 

Read DRAM

DRAM_POWER_LIMIT

Write / Read

34

0x0000

N/A

CSR:

Limit Data

Power Limit Data

 

 

 

 

DRAM_PLANE_POWER_LIM

 

 

 

 

 

 

IT

 

 

 

 

 

 

 

DRAM Power

 

 

 

 

Read sum of all

 

Limit

 

 

Accumulated DRAM

 

time durations

CSR:

Performance

38

0x0000

N/A

for which each

throttle time

DRAM_RAPL_PERF_STATUS

Status Read

 

 

 

DIMM has been

 

 

 

 

 

throttled

 

 

 

 

 

 

 

 

Notes:

1.Time, energy and power units should be assumed, where applicable, to be based on values returned by a read of the PACKAGE_POWER_SKU_UNIT MSR or through the Package Power SKU Unit PCS read service.

2.5.2.6.2DRAM Thermal Estimation Configuration Data Read/Write

This feature is relevant only when activity-based DRAM temperature estimation methods are being utilized and would apply to all the DIMMs on all the memory channels. The write allows the PECI host to configure the ‘β’ and ‘θ’ variables in Figure 2-12for DRAM channel temperature filtering as per the equation below:

TN = β ∗ TN-1+ θ ∗ ΔEnergy

TN and TN-1are the current and previous DRAM temperature estimates respectively in degrees Celsius, ‘β’ is the DRAM temperature decay factor, ‘ΔEnergy’ is the energy difference between the current and previous memory transactions as determined by the processor power control unit and ‘θ’ is the DRAM energy-to-temperature translation coefficient. The default value of ‘β’ is 0x3FF. ‘θ’ is defined by the equation:

θ= (1 - β) ∗ (Thermal Resistance) ∗ (Scaling Factor)

The ‘Thermal Resistance’ serves as a multiplier for translation of DRAM energy changes to corresponding temperature changes and may be derived from actual platform characterization data. The ‘Scaling Factor’ is used to convert memory transaction information to energy units in Joules and can be derived from system/memory configuration information. Refer to the Intel® 64 and IA-32 Architectures Software Developer’s Manual (SDM) Volumes 1, 2, and 3 for methods to program and access ‘Scaling Factor’ information.

Figure 2-12. DRAM Thermal Estimation Configuration Data

 

31

 

20

19

10

9

 

0

 

 

 

 

 

 

 

 

 

 

 

 

 

RESERVED

 

 

THETA VARIABLE

 

BETA VARIABLE

 

 

 

 

 

 

 

 

 

 

 

Memory Thermal Estimation Configuration Data

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Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

 

Datasheet Volume One

Page 40
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Intel CM8062101038606, E5-4600 Dram Thermal Estimation Configuration Data Read/Write, Limit Data, Performance, Status Read