Electrical Specifications

Table 7-6. Signals with On-Die Termination

Signal Name

Pull Up /Pull

Rail

Value

Units

Notes

Down

 

 

 

 

 

 

 

 

 

 

 

DDR{0/1}_PAR_ERR_N

Pull Up

VCCD_01

65

Ω

 

 

 

 

 

 

 

DDR{2/3}_PAR_ERR_N

Pull Up

VCCD_23

65

Ω

 

 

 

 

 

 

 

BMCINIT

Pull Down

VSS

2K

Ω

1

 

 

 

 

 

 

FRMAGENT

Pull Down

VSS

2K

Ω

1

 

 

 

 

 

 

TXT_AGENT

Pull Down

VSS

2K

Ω

1

 

 

 

 

 

 

SAFE_MODE_BOOT

Pull Down

VSS

2K

Ω

1

 

 

 

 

 

 

SOCKET_ID[1:0]

Pull Down

VSS

2K

Ω

1

 

 

 

 

 

 

BIST_ENABLE

Pull Up

VTT

2K

Ω

1

 

 

 

 

 

 

TXT_PLTEN

Pull Up

VTT

2K

Ω

1

 

 

 

 

 

 

EAR_N

Pull Up

VTT

2K

Ω

2

 

 

 

 

 

 

Notes:

1.Please refer to the applicable platform design guide to change the default states of these signals.

2.Refer to Table 7-20for details on the RON (Buffer on Resistance) value for this signal.

7.3Power-On Configuration (POC) Options

Several configuration options can be configured by hardware. The processor samples its hardware configuration at reset, on the active-to-inactive transition of RESET_N, or upon assertion of PWRGOOD (inactive-to-active transition). For specifics on these options, please refer to Table 7-7.

The sampled information configures the processor for subsequent operation. These configuration options cannot be changed except by another reset transition of the latching signal (RESET_N or PWRGOOD).

Table 7-7. Power-On Configuration Option Lands

Configuration Option

Land Name

Notes

 

 

 

Output tri state

PROCHOT_N

1

 

 

 

Execute BIST (Built-In Self Test)

BIST_ENABLE

2

 

 

 

Enable Service Processor Boot Mode

BMCINIT

3

 

 

 

Enable Intel TXT Platform

TXT_PLTEN

3

 

 

 

Power-up Sequence Halt for ITP configuration

EAR_N

3

 

 

 

Enable Bootable Firmware Agent

FRMAGENT

3

 

 

 

Enable Intel TXT Agent

TXT_AGENT

3

 

 

 

Enable Safe Mode Boot

SAFE_MODE_BOOT

3

 

 

 

Configure Socket ID

SOCKET_ID[1:0]

3

 

 

 

Notes:

1.Output tri-state option enables Fault Resilient Booting (FRB), for FRB details see Section 7.4. The signal used to latch PROCHOT_N for enabling FRB mode is RESET_N.

2.BIST_ENABLE is sampled at RESET_N de-assertion and CPU_ONLY_RESET de-assertion (on the falling edge).

3.This signal is sampled after PWRGOOD assertion.

164

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

 

Datasheet Volume One

Page 164
Image 164
Intel CM8062101038606 Power-On Configuration POC Options, Signals with On-Die Termination, Configuration Option Land Name