Intel CM8062101038606 Decoupling Guidelines, Voltage Identification VID, Power and Ground Lands

Electrical Specifications

Table 7-1. Power and Ground Lands

Power and	Number of	Comments
Ground Lands	Lands
VCC	208	Each VCC land must be supplied with the voltage determined by the
		SVID Bus signals. Table 7-3Defines the voltage level associated with
		each core SVID pattern.Table 7-11, Figure 7-2, and Figure 7-5
		represent VCC static and transient limits. VCC has a VBOOT setting of
		0.0V.
VCCPLL	3	Each VCCPLL land is connected to a 1.80 V supply, power the Phase
		Lock Loop (PLL) clock generation circuitry. An on-die PLL filter
		solution is implemented within the processor.
VCCD_01	51	Each VCCD land is connected to a switchable 1.50 V and 1.35 V supply,
VCCD_23		provide power to the processor DDR3 interface. These supplies also
		power the DDR3 memory subsystem. VCCD is also controlled by the
		SVID Bus. VCCD is the generic term for VCCD_01, VCCD_23.
VTTA	14	VTTA lands must be supplied by a fixed 1.05 V supply.
VTTD	19	VTTD lands must be supplied by a fixed 1.05 V supply.
VSA	25	Each VSA land must be supplied with the voltage determined by the
		SVID Bus signals, typically set at 0.965V. VSA has a VBOOT setting of
		0.9 V.
VSS	548	Ground

7.1.9.2Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of generating large current swings between low and full power states. This may cause voltages on power planes to sag below their minimum values if bulk decoupling is not adequate. Large electrolytic bulk capacitors (CBULK), help maintain the output voltage during current transients, for example coming out of an idle condition. Care must be taken in the baseboard design to ensure that the voltages provided to the processor remain within the specifications listed in Table 7-11. Failure to do so can result in timing violations or reduced lifetime of the processor. For further information, refer to the appropriate Platform Design Guide (PDG).

7.1.9.3Voltage Identification (VID)

The Voltage Identification (VID) specification for the VCC, VSA, VCCD voltage are defined by the VR12/IMVP7 Pulse Width Modulation Specification. The reference voltage or the VID setting is set via the SVID communication bus between the processor and the voltage regulator controller chip. The VID settings are the nominal voltages to be delivered to the processor's VCC, VSA, VCCD lands. Table 7-3specifies the reference voltage level corresponding to the VID value transmitted over serial VID. The VID codes will change due to temperature and/or current load changes in order to minimize the power and to maximize the performance of the part. The specifications are set so that a voltage regulator can operate with all supported frequencies.

Individual processor VID values may be calibrated during manufacturing such that two processor units with the same core frequency may have different default VID settings.

The processor uses voltage identification signals to support automatic selection of VCC, VSA, and VCCD power supply voltages. If the processor socket is empty (SKTOCC_N high), or a “not supported” response is received from the SVID bus, then the voltage regulation circuit cannot supply the voltage that is requested, the voltage regulator must disable itself or not power on. Vout MAX register (30h) is programmed by the processor to set the maximum supported VID code and if the programmed VID code is

156	Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
	Datasheet Volume One