Signal Descriptions

Table 6-4. PCI Express* Port 2 Signals (Sheet 2 of 2)

Signal Name

Description

PE2D_RX_DN[15:12]

PCIe* Receive Data Input

PE2D_RX_DP[15:12]

 

 

 

PE2A_TX_DN[3:0]

PCIe* Transmit Data Output

PE2A_TX_DP[3:0]

 

 

 

PE2B_TX_DN[7:4]

PCIe* Transmit Data Output

PE2B_TX_DP[7:4]

 

 

 

PE2C_TX_DN[11:8]

PCIe* Transmit Data Output

PE2C_TX_DP[11:8]

 

 

 

PE2D_TX_DN[15:12]

PCIe* Transmit Data Output

PE2D_TX_DP[15:12]

 

 

 

Table 6-5. PCI Express* Port 3 Signals

Signal Name

Description

PE3A_RX_DN[3:0]

PCIe* Receive Data Input

PE3A_RX_DP[3:0]

 

 

 

PE3B_RX_DN[7:4]

PCIe* Receive Data Input

PE3B_RX_DP[7:4]

 

 

 

PE3C_RX_DN[11:8]

PCIe* Receive Data Input

PE3C_RX_DP[11:8]

 

 

 

PE3D_RX_DN[15:12]

PCIe* Receive Data Input

PE3D_RX_DP[15:12]

 

 

 

PE3A_TX_DN[3:0]

PCIe* Transmit Data Output

PE3A_TX_DP[3:0]

 

 

 

PE3B_TX_DN[7:4]

PCIe* Transmit Data Output

PE3B_TX_DP[7:4]

 

 

 

PE3C_TX_DN[11:8]

PCIe* Transmit Data Output

PE3C_TX_DP[11:8]

 

 

 

PE3D_TX_DN[15:12]

PCIe* Transmit Data Output

PE3D_TX_DP[15:12]

 

 

 

Table 6-6. PCI Express* Miscellaneous Signals (Sheet 1 of 2)

Signal Name

Description

 

 

This input is used to control PCI Express* bias currents. A 50 ohm

 

 

1% tolerance resistor must be connected from this land to VSS by

 

PE_RBIAS

the platform. PE_RBIAS is required to be connected as if the link is

 

 

being used even when PCIe* is not used. Refer to the appropriate

 

 

Platform Design Guide (PDG) for further details.

 

 

 

 

 

 

 

Provides dedicated bias resistor sensing to minimize the voltage

 

 

 

drop caused by packaging and platform effects. PE_RBIAS_SENSE

 

PE_RBIAS_SENSE

is required to be connected as if the link is being used even when

 

 

PCIe* is not used. Refer to the appropriate Platform Design Guide

 

 

(PDG) for further details.

 

 

 

 

 

 

PCI Express* voltage reference used to measure the actual output

 

PE_VREF_CAP

voltage and comparing it to the assumed voltage. A 0.01uF

 

 

 

capacitor must be connected from this land to VSS.

 

 

 

 

 

 

PCI Express* Hot-Plug SMBus Clock: Provides PCI Express* hot-

 

PEHPSCL

plug support via a dedicated SMBus interface. Requires an external

 

general purpose input/output (GPIO) expansion device on the

 

 

 

 

 

 

platform.

 

 

 

 

 

Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families

145

Datasheet Volume One

 

 

Page 145
Image 145
Intel E5-4600 PCI Express* Port 2 Signals Sheet 2, PCI Express* Port 3 Signals, PCI Express* Miscellaneous Signals Sheet 1