Panasonic MN101C77C, F77G user manual TM6ICR TM6IE TM6IR LV1

Chapter 3 Interrupts

■Timer 6 Interrupt Control Register (TM6ICR)

The timer 6 interrupt control register (TM6ICR) controls interrupt level of timer 6 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0".

TM6ICR

7	6	5	4	3	2	1	0
TM6	TM6	-	-	-	-	TM6IE	TM6IR
LV1	LV0

(At reset : 0 0 - - - - 0 0)

TM6IR Interrupt request flag

0No interrupt request

1Interrupt request generated

TM6IE Interrupt enable flag

0Disable interrupt

1Enable interrupt

TM6	TM6	Interrupt level flag
LV1	LV0

The CPU has interrupt levels from 0 to 3. These flags set the interrupt level for interrupt requests.

Figure 3-2-14 Timer 6 Interrupt Control Register (TM6ICR : x'03FEF', R/W)

III- 26 Control Registers