Panasonic MN101C77C, F77G user manual Pin Function Summary 2/6

Chapter 1 Overview

Table 1-3-4 Pin Function Summary (2/6)

Name	No.	I/O	Function	Other Function	Description
P20	27	I/O	I/O port 2	IRQ0	5-Bit CMOS tri-state I/O port.
P21	28			IRQ1, ACZ	A pull-up resistor for each bit can be selected
					individually by the P2PLU register.
P22	29			IRQ2
					At reset, pull-up resistors are disabled
P23	30			IRQ3
					(high impedance output).
P24	31			IRQ4
P27	14	Input	I/O port 2	NRST	P27 has an n-channel open-drain configuration.
					When "0" is written and the reset is initiated by
					software, a low level will be output.
P50	32	I/O	I/O port 5	SBI3	5-Bit CMOS tri-state I/O port.
P51	33			SBO3,	Each bit can be set individually as either an input
					or output by the P5DIR register. A pull-up resistor
P52	34			SBT3
					for each bit can be selected individually by the
P53	35			SDA4A
					P5PLU register. At reset, the P50t o P54 input
					mode is selected and pull- up resistors are
P54	36			SCL4A	disabled. (high impedance output)
P60	37	I/O	I/O port 6	SDO0, KEY0	8-Bit CMOS tri-state I/O port.
P61	38			SDO1, KEY1	Each bit can be set individually as either an input
					or output by the P6DIR register. A pull-up resistor
P62	39			SDO2, KEY2
					for each bit can be selected individually by the
P63	40			SDO3, KEY3
					P6PLU register.
P64	41			SDO4, KEY4	At reset, the P60 to P67 input mode is selected
P65	42			SDO5, KEY5	and pull- up resistors are disabled.
					(high impedance output)
P66	43			SDO6, KEY6
P67	44			SDO7, KEY7
P70	45	I/O	I/O port 7	SBO0B, TXD0B	8-Bit CMOS tri-state I/O port.
P71	46			SBI0B, RXD0B	Each bit can be set individually as either an input
					or output by the P7DIR register. A pull-up/pull-
P72	47			SBT0B
					down resistor for each bit can be selected
P73	48			SBO1B, TXD1B
					individually by the P7PLU register. However,
P74	49			SBI1B, RXD1B	pull-up and pull-down resistors cannot be mixed.
P75	50			SBT1B	At reset, the P70to P77 input mode is selected
					and pull- up resistors are disabled. (high
P76	51			TCI01
					impedance output)
P77	52			TCI05
P80	60	I/O	I/O port 8	LED0	8-Bit CMOS tri-state I/O port. Each bit can be set
P81	59			LED1	individually as either an input or output by the
					P8DIR register. A pull-up resistor for each bit can
P82	58			LED2
					be selected individually by the P8PLU register.
P83	57			LED3	When configured as outputs, these pins can
P84	56			LED4	drive LEDs directly. At reset, the P80to P87 input
P85	55			LED5	mode is selected and pull- up resistors are
					disabled. (high impedance output)
P86	54			LED6
P87	53			LED7
PA0	62	I/O	I/O port A	AN0, DA0	6-Bit I/O port. A pull-up or pull-down resistor for
PA1	63			AN1, DA1	each bit can be selected individually by the
					PAPLUD resister. However, pull-up and pull-
PA2	64			AN2
					down resistors cannot be mixed. At reset, the
PA3	1			AN3
					PA0 to PA6 input mode is selected and pull- up
PA4	2			AN4	resistors are disabled. (high impedance output)
PA5	3			AN5
PA6	4			AN6

I - 12 Pin Description