Panasonic MN101C77C, F77G user manual Processor Status WordPSW

Chapter 2 CPU Basics

2-1-7 Processor Status Word

Processor status word (PSW) is an 8-bit register that stores flags for operation results, interrupt mask level, and maskable interrupt enable. PSW is automatically pushed onto the stack when an interrupt occurs and is automatically popped when return from the interrupt service routine.

PSW

7	6	5		4	3	2	1	0
Reserved	MIE		IM1	IM0	VF	NF	CF	ZF

( At reset : 0 0 0 0 0 0 0 0 )

ZF Zero flag

0Operation result is not "0".

1Operation result is "0".

CF Carry flag

0A carry or a borrow from MSB did not occur.

1	A carry or a borrow from MSB
	occured.
NF Negative flag

0MSB of operation results is "0".

1MSB of operation results is "1".

VF Overflow flag

0Overflow did not occur.

1Overflow occured.

IM1 to 0 Interrupt mask level

Controls maskable interrupt acceptance.

MIE Maskable interrupt enable

0

All maskable interrupts are disabled.

1(xxxLVn,xxxIE) for each interrupt are enabled.

Reserved

Set always "0".

Figure 2-1-3 Processor Status Word(PSW)

II - 8 Overview