Panasonic MN101C77C, F77G user manual TM0IE, TM1IE

Chapter 6 8-bit Timers

Setup Procedure					Description
(7) Disable the lower timer interrupt.			(7) Set the TM0IE flag of the timer 0 interrupt
TM0ICR (x'3FE9')				control register (TM0ICR) to "0" to disable the
bp1	:TM0IE	= 0		interrupt.
(8) Set the level of the upper timer			(8) Set the interrupt level by the TM1LV1-0 flag of
interrupt.				the timer 1 interrupt control register (TM1ICR).
TM1ICR (x'3FEA')				If any interrupt request flag may be already
bp7-6	:TM1LV1-0	= 10		set, clear all request flags.
				[	Chapter 3 3-1-4. Interrupt Flag Setup ]
(9) Enable the upper timer interrupt.			(9)	Set the TM1IE flag of the TM1ICR register to
TM1ICR (x'3FEA')				"1" to enable the interrupt.
bp1	:TM1IE	= 1
(10) Start the upper timer operation.			(10) Set the TM1EN flag of the TM1MD register to
TM1MD (x'3F55')				"1" to start timer 1.
bp3	:TM1EN	= 1
(11) Start the lower timer operation.			(11) Set the TM0EN flag of the TM0MD register to
TM0MD (x'3F54')				"1" to start timer 0.
bp3	:TM0EN	= 1

TM1BC + TM0BC counts up from x'0000' as a 16-bit timer. When TM1BC + TM0BC reaches the set value of TM1OC + TM0OC register, the timer 1 interrupt request flag is set to "1" at the next count clock, and the value of TM1BC + TM0BC becomes x'0000' and counting up is restarted.

Use a 16-bit access instruction to set the (TM1OC + TM0OC) register.

Start the upper timer operation before the lower timer operation.

VI - 42 Cascade Connection