Panasonic MN101C77C, F77G user manual Cpu

Chapter 2 CPU Basics

High-frequency

Low-frequency

.

.

4

2

fosc

1

CPU

.		11			.
	2	0		0
					.		00
			11
		1		1		4			System Clock
.							01
		OSCDBL
				OSC0		16				fs
							1*
	2							.

fx 0

SOSC2DS

0

1

OSCSEL[1:0]

SOSCDBL

Figure 2-5-3 Clock Switching Circuit

			Division factor for
OSCSEL1	OSCSEL0	OSCDBL	High-frequency (OSC) Input
			(NORMAL mode)
0	0	0	2
0	0	1	1
0	1	0	8
0	1	1	4
1	0	0	32
1	0	1	16
1	1	0	64
1	1	1	64

Figure 2-5-4 Setting Division Factor at NORMAL mode

by combination of OSCSEL and OSCDBL

				Division factor for
OSCSEL1	OSCSEL0	SOSCDBL	SOSC2DS	Low-frequency (XI / XO) Input
				(SLOW mode)
0	0	0	0	2
0	0	0	1	4
0	0	1	0	1
0	0	1	1	2
0	1	1	0	4

Figure 2-5-5 Setting Division Factor at SLOW mode

by combination of OSCSEL and SOSC2DS

On clock switching, set each flag of OSCDBL, OSCSEL, SOSCSEL and OSC0, individually. Even if those flags are mapped on the same special functions register, set twice.

Set the OSC0 flag to "0" (NORMAL mode) before switching of division factor for low-frequency input.

Set the division factor in SLOW mode only to 1 to 4 division and do not set other values.

II- 26 Clock Switching