Panasonic F77G, MN101C77C user manual Block Diagram and Function

Chapter 2 CPU Basics

2-1-1 Block Diagram

Data registers

		D0	Processor status word	T1	Clock	Source oscillation
	Address registers	D1	PSW	T2	generator
Stack pointer	A0	D2
SP	A1	D3
ABUS					Instruction execution
					controller
BBUS
	Program				Instruction decoder
	counter
	Incrementer
		ALU
					Instruction	Interrupt
					queue	controller
Program address			Operand address			Interrupt bus

Bus controller

ROM bus

RAM bus

Peripheral expansion bus

Internal ROM

Internal RAM

Internal peripheral

functions

Clock generator	Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals
	to CPU blocks.
	Generates addresses for the instructions to be inserted into the instruction queue. Normally
Program counter	incremented by sequencer indication, but may be set to branch destination address or ALU operation
	result when branch instructions or interrupts occur.
Instruction queue	Stores up to 2 bytes of pre-fetched instructions.
Instruction decoder	Decodes the instruction queue, sequentially generates the control signals needed for instruction
	execution, and executes the instruction by controlling the blocks within the chip.
Instruction execution	Controls CPU block operations in response to the result decoded by the instruction decoder and
controller	interrupt requests.
ALU	Executes arithmetic operations, logic operations, shift operations, and calculates operand addresses
	for register relative indirect addressing mode.
Internal ROM, RAM	Assigned to the execution program, data and stack region.
Address register	Stores the addresses specifying memory for data transfer. Stores the base address for register relative
	indirect addressing mode.
Data register	Holds data for operations. Two 8-bit registers can be connected to form a 16-bit register.
Interrupt controller	Detects interrupt requests from peripheral functions and requests CPU shift to interrupt processing.
Bus controller	Controls connection of CPU internal bus and CPU external bus. Includes bus usage arbitration
	function.
Internal peripheral	Includes peripheral functions (timer, serial interface, A/D converter, D/A converter, etc.) Peripheral
functions	functions vary with model.

Figure 2-1-1 Block Diagram and Function

Overview II - 3