Panasonic MN101C77C, F77G user manual Tbicr, If the interrupt request flag had already been, Tbie

Chapter 8 Time Base Timer / 8-bit Free-running Timer

8-4-2 Setup Example

„Timer Operation Setup (Time Base Timer)

An interrupt can be generated constantly with time base timer in the selected interrupt cycle. The inter- rupt generation cycle is as fosc ⋅ 1/213 (as 0.977 ms : fosc = 8.38 MHz) for generation interrupts.

An example setup procedure, with a description of each step is shown below.

	Setup Procedure					Description
(1)	Select the clock source.			(1)	Select fosc as a clock source by the TM6CK0
	TM6MD (x'3F6A')				flag of the timer 6 mode register (TM6MD).
	bp0	: TM6CK0	= 0
(2)	Select the interrupt generation			(2)	Select the selected clock ⋅ 1/213 as an interrupt
	cycle.				generation cycle by the TM6IR2-0 flag of the
	TM6MD (x'3F6A')				TM6MD register.
	bp6-4	: TM6IR2-0	= 100
(3)	Initialize the time base timer.			(3)	Write value to the time base timer clear control
	TBCLR (x'3F6B')		= x'00'		register (TBCLR) to initialize the time base
					timer. That makes the time base timer initialize.
(4)	Set the interrupt level.			(4)	Set the interrupt level by the TBLV1-0 flag of
	TBICR (x'3FF0')				the time base interrupt control register
	bp7-6	: TBLV1-0	= 01		(TBICR).
					If the interrupt request flag had already been
					set, clear it.
					[	Chapter 3 3-1-4. Interrupt Flag Setup ]
(5)	Enable the interrupt.			(5)	Set the TBIE flag of the TBICR register to "1"
	TBICR (x'3FF0')				to enable the interrupt.
	bp1	: TBIE	= 1

* the above steps (1), (2) can be set at once.

When the selected interrupt generation cycle has passed, the interrupt request flag of the time base interrupt control register (TBICR) is set to "1".

VIII - 14 Time Base Timer