Panasonic MN101C77C „Reception Timing, Reception Timing rising edge, start condition is enabled

Chapter 11 Serial Interface 0, 1

„Reception Timing

(at master) Tmax=2.5 T T

Clock (SBT pin)

Input data (SBI pin)

Transfer bit counter 0 1 2 3 4 5 6 7

SCnRBSY

∆

(Write data to TXBUFn) Interrupt

(SCnTIRQ)

Figure 11-3-9 Reception Timing (rising edge, start condition is enabled)

(at master)

Tmax=1.5 T T

Clock (SBT pin)

Input data (SBI pin)

Transfer bit counter 0 1 2 3 4 5 6 7

SCnRBSY

∆

(Write data to TXBUFn) Interrupt

(SCnTIRQ)

Figure 11-3-10 Reception Timing (rising edge, start condition is disabled)

XI - 30 Operation