Panasonic MN101C77C, F77G user manual „Count Timing of Timer Pulse Output Timer

Chapter 7 16-bit Timer

„Count Timing of Timer Pulse Output (Timer 7)

Count clock

TM7EN flag

Compare

N

register 1

Binary	0000 0001	N-1 N 0000 0001	N-1 N 0000 0001	N-1 N 0000
counter

Interrupt request flag

TM7IO output

Figure 7-5-1 Count Timing of Timer Pulse Output (Timer 7)

The TM7IO pin outputs 2 x cycle, compared to the value in the compare register 1. If the binary counter reaches the compare register, and the binary counter is cleared to x'0000' or the full count overflow, the TM7IO output (timer output) is inverted. The inversion of the timer output is changed at the rising edge of the count clock. This is happened to form the waveform inside to correct the output cycle.

In the initial state after releasing reset, the timer pulse output is reset, and low output is fixed. Therefore, release the reset of the timer pulse output by setting the TM7CL flag of the TM7MD1 register to "0".

VII - 20 16-bit Timer Pulse Output