Panasonic MN101C77C, F77G user manual External Interrupt 3 Control Register IRQ3ICR x03FE5, R/W

Chapter 3 Interrupts

■External Interrupt 3 Control Register (IRQ3ICR)

The external interrupt 3 control register (IRQ3ICR) controls interrupt level of external interrupt 3, active edge, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".

IRQ3ICR

7	6	5	4	3	2	1	0
IRQ3	IRQ3	REDG3	-	-	-	IRQ3IE	IRQ3IR
LV1	LV0

(At reset : 0 0 0 - - - 0 0)

IRQ3IR External interrupt request flag

0No interrupt request

1Interrupt request generated

IRQ3IE External interrupt enable flag

0Disable interrupt

1Enable interrupt

REDG3 External interrupt active edge flag

0Falling edge

1Rising edge

IRQ3	IRQ3	Interrupt level flag for external interrupt
LV1	LV0

The CPU has interrupt levels from 0 to 3. These flags set the interrupt level for interrupt requests

Figure 3-2-5 External Interrupt 3 Control Register (IRQ3ICR : x'03FE5', R/W)

III- 20 Control Registers