Chapter 3 Interrupts

Time Base Interrupt Control Register (TBICR)

The time base interrupt control register (TBICR) controls interrupt level of time base interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0".

TBICR

7

6

5

4

3

2

1

0

 

TB

TB

-

-

-

-

TBIE

TBIR

 

LV1

LV0

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

(At reset : 0 0 - - - - 0 0)

TBIR

Interrupt request flag

 

 

0No interrupt request

1Interrupt request generated

TBIE

Interrupt enable flag

0Disable interrupt

1Enable interrupt

TB

TB

Interrupt level flag

LV1

LV0

 

 

 

 

The CPU has interrupt levels from 0 to 3. These flags set the interrupt level for interrupt requests.

Figure 3-2-15 Time Base Interrupt Control Register (TBICR : x'03FF0', R/W)

Control Registers

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Panasonic F77G, MN101C77C user manual Time Base Interrupt Control Register Tbicr x03FF0, R/W, Tbicr Tbie Tbir LV1