Panasonic MN101C77C, F77G user manual Xvii 12 Special Function Registers List

Chapter 17 Appendices

Address	Register			Bit Symbol /Initial Value /Description							Page
		Bit 7	Bit 6	Bit 5	Bit 4	Bit 3		Bit 2	Bit 1	Bit 0
		-	Reserved	-	-	-		-	SC3ODC1	SC3ODC0
X'3FAE'	SC3ODC		Set Always						P52	P51	XII - 9
			to "0"						Output Type	Output Type
									Selection	Selection
		-	-	-	-	-		SC3PSC2	SC3PSC1	SC3PSC0	V - 10
X'3FAF'	SC3CKS
								Serial 3 Transfer Clock Selection
											XII - 9
								(Prescaler Output)
		ANSH1	ANSH0	ANCK1	ANCK0	ANLADE		-	-	-
X'3FB0'	ANCTR0										XV - 5
		A/D Sample Hold		A/D Conversion Clock		A/D Rudder
		Timer Setup		Selection		Resistance
						Control
		-	-	-	-	Reserved		ANCHS2	ANCHS1	ANCHS0
X'3FB1'	ANCTR1										XV - 6
						Set Always		Analog Input Channel Selection
						to "0"
		ANST	ANSTSEL	-	-	-		-	-	-
X'3FB2'	ANCTR2										XV - 6
		A/D Conversion	A/D Conversion
		Status	Start Factor
			Selection
		ANBUF07	ANBUF06	-	-	-		-	-	-
X'3FB3'	ANBUF0										XV - 7
		A/D Conversion Data Storage
		Register (Lower 2 bits)
		ANBUF17	ANBUF16	ANBUF15	ANBUF14	ANBUF13		ANBUF12	ANBUF11	ANBUF10
X'3FB4'	ANBUF1										XV - 7
					A/D Conversion Data Storage
					Register (Upper 8 bits)
		-	-	-	-	-		DABUSY	DACH1	DACH0
X'3FBE'	DACTR						D/A Conversion		PA1	PA0	XVI - 5
								Enable Flag	Output Type	Output Type
									Selection	Selection
		DA01BUF7	DA01BUF6	DA01BUF5	DA01BUF4	DA01BUF3		DA01BUF2	DA01BUF1	DA01BUF0
X'3FBF'	DADR01										XVI - 6
				D/A Conversion Data Storage Register
		RC0APL7	RC0APL6	RC0APL5	RC0APL4	RC0APL3		RC0APL2	RC0APL1	RC0APL0
X'3FC7'	RC0APL										II - 33
				ROM Correction Address 0 Setting Register				Lower 8 bits
		RC0APM7	RC0APM6	RC0APM5	RC0APM4	RC0APM3		RC0APM2	RC0APM1	RC0APM0
X'3FC8'	RC0APM										II - 33
				ROM Correction Address 0 Setting Register				Middle 8 bits
		-	-	-	-	-		-	RC0APH1	RC0APH0
X'3FC9'	RC0APH										II - 33
				ROM Correction Addreess 0 Setting Register Upper 2 bits
		RC1APL7	RC1APL6	RC1APL5	RC1APL4	RC1APL3		RC1APL2	RC1APL1	RC1APL0
X'3FCA'	RC1APL										II - 33
				ROM Correction Address 1 Setting Register Lower 8 bits
		RC1APM7	RC1APM6	RC1APM5	RC1APM4	RC1APM3		RC1APM2	RC1APM1	RC1APM0
X'3FCB'	RC1APM										II - 33
				ROM Correction Address 1 Setting Register				Middle 8 bits
		-	-	-	-	-		-	RC1APH1	RC1APH0
X'3FCC'	RC1APH			ROM Correction Addreess 1 Setting Register Upper 2 bits							II - 33
		RC2APL7	RC2APL6	RC2APL5	RC2APL4	RC2APL3		RC2APL2	RC2APL1	RC2APL0
X'3FCD'	RC2APL			ROM Correction Address 2 Setting Register Lower 8 bits							II - 34
		RC2APM7	RC2APM6	RC2APM5	RC2APM4	RC2APM3		RC2APM2	RC2APM1	RC2APM0
X'3FCE'	RC2APM			ROM Correction Address 2 Setting Register				Middle 8 bits			II - 34
		-	-	-	-	-		-	RC2APH1	RC2APH0
X'3FCF'	RC2APH										II - 34
				ROM Correction Addreess 2 Setting Register Upper 2 bits
		FMODE	AT1ACT	ATMD3	ATMD2	ATMD1		ATMD0	Reserved	AT1EN
X'3FD0'	ATCNT0	Pointer 0	ATC1 Program	ATC1 Data Transfer Mode Selection					Set Always	ATC1 Transfer	XIV - 6
		Increment	Activation Flag						to "0"	Enable
		Control

XVII - 12 Special Function Registers List