Panasonic MN101C77C, F77G user manual Synchronous Serial Interface Internal Clock Source

Chapter 12 Serial Interface 3

„Continuous Communication

Serial interface 3 can be started by automatic data transfer function ATC1, built-in this LSI. If ATC1 is used for activation, data can be continuously transferred up to 255 byte. The communication blank, from the generation of the communication complete interrupt SC3IRQ to the generation of the next transfer clock, is up to 18 machine cycles + 2 transfer clocks. For activation by ATC1, refer to chapter 14 Auto- matic Transfer Controller, Transfer mode 6 to 7.

If start condition is input for activation again, during communication, the transmission data be- comes invalid. If the transmission should be operated again, set the transmission data to SC3TRB, again.

„Clock Setup

Clock source is selected from the dedicated prescaler by the SC3CKS register and timer 5 output. The dedicated prescaler is started by selecting "prescaler operation" by the PSCMD (x'03F6F') register. The SC3MST flag of the SC3MD1 register can select the internal clock (clock master), or the external clock (clock slave). Even if the external clock is selected, the internal clock with same frequency to the external clock, should be set by the SC3CKS register, because the internal clock generates the interrupt flag SC3IRQ. Table 12-3-2 shows the internal clock source which can be set by the SC3CKS register.

Table 12-3-2 Synchronous Serial Interface Internal Clock Source

Communication type	Clcok synchronous
	fosc/2
	fosc/4
Clock source
	fosc/16
(internal clock)
	fosc/32
	fs/2
	fs/4
	timer 5 output

„BUSY Flag

If data is set to the transmit/receive shift register SC3TRB, or start condition is enabled, the busy flag SC3BSY is set. That is cleared by the generation of the communication complete interrupt SC3IRQ.

„Input edge/Output edge Setup

The SC3CE1 flag of the SC3MD0 register can set the output edge of the transmission data, and the input edge of the received data. Data at transmission is output at the falling edge of clock as the SC3CE1 flag

="0", and at the rising edge of clock as the SC3CE1 = "1". Data at reception is input at the rising edge of clock as the SC3CE1 = "0", and at the falling edge of clock as the SC3CE1 flag = "1".

XII - 12 Operation