Panasonic MN101C77C, F77G user manual bit PWM Output, Output Pins of PWM Output

Models: F77G MN101C77C

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Chapter 6 8-bit Timers

6-6 8-bit PWM Output

The TMnIO pin outputs the PWM waveform, which is determined by the match timing for the compare register and the overflow timing of the binary counter.

6-6-1 Operation

„Operation of 8-bit PWM Output (Timers 0, 4 and 5)

The PWM waveform with any duty cycle is generated by setting the duty cycle of PWM "H" period to the compare register (TMnOC). The cycle is the period from the full count to the overflow of the 8-bit timer. Table 6-6-1 shows PWM output pins ;

Table 6-6-1 Output Pins of PWM Output

 

Timer 0

Timer 4

Timer 5

 

 

 

 

PWM output pin

TM0IO output pin

TM4IO output pin

TM5IO output pin

(P10, P11)

(P12, P13)

(P52)

 

„Count Timing of PWM Output (at normal) (Timers 0, 4 and 5)

Count clock

TMnEN flag

Compare register

Binary counter

PWM source wave form

TMnIO output (PWM output)

N

00

01

N-1 N N+1 N+2

FE FF 00 01

N-1 N N+1

(A)

 

(B)

(C)

 

Set time in the compare register

 

 

 

PWM basic components ( overflow time of binary counter)

 

Figure 6-6-1 Count Timing of PWM Output (at Normal)

PWM source waveform,

(A)is "H" while counting up from x'00' to the value stored in the compare register.

(B)is "L" after the match to the value in the compare register, then the binary counter continues counting up till the overflow.

(C)is "H" again, if the binary counter overflow.

The PWM outputs the PWM source waveform with 1 count clock delay. This is happened, because the waveform is created inside to correct the output cycle.

VI - 26 8-bit PWM Output

Page 240
Image 240
Panasonic MN101C77C, F77G bit PWM Output, Output Pins of PWM Output, „Count Timing of PWM Output at normal Timers 0, 4