Panasonic MN101C77C, F77G user manual Reception Timing parity bit is enabled

Chapter 11 Serial Interface 0, 1

„Reception Timing

Tmin=0.5 T	T
	Parity	Stop	Stop
RXD pin	bit	bit	bit

SCnRBSY

∆

input start condition

Interrupt (SCnRIRQ)

Figure 11-3-18 Reception Timing (parity bit is enabled)

Tmin=0.5T	T
	stop	stop
RXD pin	bit	bit

SCRBSY

∆

input start condition

Interrupt (SCRIRQ)

Figure 11-3-19 Reception Timing (parity bit is disabled)

XI - 50 Operation