Panasonic MN101C77C, F77G user manual SC3ICR SC3IE SC3IR LV1 LV0

Chapter 3 Interrupts

■Serial Interface 3 Interrupt Control Register (SC3ICR)

The serial interface 3 interrupt control register (SC3ICR) controls interrupt level of serial interface 3 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".

SC3ICR

7	6	5	4	3	2	1	0
SC3	SC3	-	-	-	-	SC3IE	SC3IR
LV1	LV0

(At reset : 0 0 - - - - 0 0)

SC3IR Interrupt request flag

0No interrupt request

1Interrupt request generated

SC3IE Interrupt enable flag

0Disable interrupt

1Enable interrupt

SC3	SC3	Interrupt level flag
LV1	LV0

The CPU has interrupt levels from 0 to 3. These flags set the interrupt level for interrupt requests.

Figure 3-2-23 Serial Interface 3 Interrupt Control Register (SC3ICR : x'03FF9', R/W)

III- 34 Control Registers