Panasonic MN101C77C, F77G Interrupt Flag Setup, Interrupt request flag IR setup by the software

Models: F77G MN101C77C

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Chapter 3 Interrupts

3-1-4 Interrupt Flag Setup

Interrupt request flag (IR) setup by the software

The interrupt request flag is operated by the hardware. That is set to "1" when any interrupt factor is generated, and cleared to "0" when the interrupt is accepted. If you want to operate it by the software, the IRWE flag of MEMCTR should be set to "1".

Interrupt flag setup procedure

A setup procedure of the interrupt request flag set by the hardware and the software shows as follows ;

 

Setup Procedure

 

Description

 

 

 

 

(1)

Disable all maskable interrupts.

(1)

Clear the MIE flag of PSW to disable all

 

PSW

 

maskable interrupts. This is necessary,

 

bp6 : MIE = 0

 

especially when the interrupt control register is

 

 

 

changed.

(2)

Select the interrupt factor.

(2)

Select the interrupt factor such as interrupt

 

 

 

edge selection, or timer interrupt cycle change.

(3)

Enable the interrupt request flag to

(3)

Set the IRWE flag of MEMCTR to enable the

 

be rewritten.

 

interrupt request flag to be rewritten. This is

 

MEMCTR (x'3F01')

 

necessary only when the interrupt request flag

 

bp2 : IRWE = 1

 

is changed by the software.

(4)

Rewrite the interrupt request flag.

(4)

Rewrite the interrupt request flag (xxxIR) of the

 

xxxICR

 

interrupt control register (xxxICR).

 

bp0 : xxxIR

 

 

(5)

Disable the interrupt request flag to

(5)

Clear the IRWE flag so that interrupt request

 

be rewritten.

 

flag can not be rewritten by the software.

 

MEMCTR (x'3F01')

 

 

 

bp2 : IRWE = 0

 

 

(6)

Set the interrupt level.

(6)

Set the interrupt level by the xxxLV1-0 flag of

 

xxxICR

 

the interrupt control register (xxxICR).

 

bp7-6 : xxxLV1-0

 

Set the IM1-0 flag of PSW when the interrupt

 

PSW

 

acceptance level of CPU should be changed.

 

bp5-4 : IM1-0

 

 

(7)

Enable the interrupt.

(7)

Set the xxxIE flag of the interrupt control

 

xxxICR

 

register (xxxICR) to enable the interrupt.

 

bp1 : xxxIE = 1

 

 

(8)

Enable all maskable interrupts.

(8)

Set the MIE flag of PSW to enable maskable

 

PSW

 

interrupts.

 

bp6 : MIE = 1

 

 

 

 

 

 

III - 14

Overview

 

 

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Panasonic MN101C77C Interrupt Flag Setup, Interrupt request flag IR setup by the software, Interrupt flag setup procedure