Panasonic F77G, MN101C77C user manual Bus Interface, Bus Controller

Chapter 2 CPU Basics

2-3 Bus Interface

2-3-1 Bus Controller

The MN101C series provides separate buses to the internal memory and internal peripheral circuits to reduce bus line loads and thus realize faster operation.

There are three such buses: ROM bus, RAM bus, and peripheral expansion bus (I/O bus). They connect to the internal ROM, internal RAM, and internal peripheral circuits respectively. The bus control block controls the parallel operation of instruction read and data access. A functional block diagram of the bus controller is given below.

Instruction							Interrupt
queue		Program address	Operand address				control
		Bus controller
						Memory control register		Interrupt
								bus
		Address decode				Memory mode setting
					Bus
						Bus access (wait)
					arbitor
						control
ROM bus			RAM bus			Peripheral
						extension bus
A	D		A	D		A	D
			Internal RAM			Internal
						peripheral functions

Internal ROM

Figure 2-3-1 Functional Block Diagram of the Bus Controller

Bus Interface II - 15