Panasonic F77G, MN101C77C user manual Synchronous Output Timing by Event Generation IRQ2

Chapter 4 I/O Ports

„Port 6 Synchronous Output (External interrupt 2 IRQ2))

The synchronous output timing when the synchronous output event is set at the falling edge of the external interrupt 2, is shown below. The latched data on port 6 is output in synchronization with the falling edge of the IRQ2.

Port 6 output	X	Y	Z	X	Y
latched data
External interrupt
(IRQ2)
Port 6 output		X	Y	Z	Y

Figure 4-11-2 Synchronous Output Timing by Event Generation (IRQ2)

„Port 6 Synchronous Output (Timers 1,5 and 7)

The timer interrupt flag TMnIRQ is generated when binary counter and compare register are matched. The latched data on port 6 is output from the port 6 in synchronization with the rising edge of the TMnIRQ. About the setting of each timer operation, refer to chapter 6. 8-Bit timers, and chapter 7. 16-Bit timers.

Timer count clock

Timer compare			N
register
Binary counter	N-1 N	00 01	N-1 N 00 01	N-1 N	00 01	N-1
Port 6 output	X	Y	Z	X	Y
latched data
Interrupt request
flag
Port 6 output	X		Y	Z		Y

Figure 4-11-3 Synchronous Output Timing by Event Generation (Timers 1, 5 and 7)

Synchronous Output (Port 7) IV - 51