Panasonic MN101C77C, F77G user manual TM0ICR TM0IE TM0IR LV1

Chapter 3 Interrupts

■Timer 0 Interrupt Control Register (TM0ICR)

The timer 0 interrupt control register (TM0ICR) controls interrupt level of timer 0 interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable inter- rupt enable flag (MIE) of PSW is "0".

TM0ICR

7	6	5	4	3	2	1	0
TM0	TM0	-	-	-	-	TM0IE	TM0IR
LV1	LV0

(At reset : 0 0 - - - - 0 0)

TM0IR Interrupt request flag

0No interrupt request

1Interrupt request generated

TM0IE Interrupt enable flag

0Disable interrupt

1Enable interrupt

TM0	TM0	Interrupt level flag
LV1	LV0

The CPU has interrupt levels from 0 to 3. These flags set the interrupt level for interrupt requests.

Figure 3-2-8 Timer 0 Interrupt Control Register (TM0ICR : x'03FE9', R/W)

III- 22 Control Registers