Panasonic MN101C77C, F77G user manual SC1RIR, SC1RIE SC1R SC1R LV1 LV0

Chapter 3 Interrupts

■Serial Interface 1 Reception Interrupt Control Register (SC1ICR)

The serial Interface 1 reception interrupt control register (SC1ICR) controls interrupt level of serial Interface 1 reception interrupt, interrupt enable flag and interrupt request. Interrupt control register should be operated when the maskable interrupt enable flag (MIE) of PSW is "0".

	7	6	5	4	3	2	1	0
SC1RICR	SC1R	SC1R	-	-	-	-	SC1RIE SC1RIR		(at reset : 0 0 - - - - 0 0 )
	LV1	LV0
									SC1RIR	Serial interface 1 reception
										interrupt request flag
									0	No interrupt request flag
									1	Interrupt request generated

SC1RIE

0

1

SC1R SC1R

LV1 LV0

Serial interface 1 reception interrupt enable flag

Disable interrupt

Enable interrupt

Serial interface 1 reception interrupt level flag

The CPU has interrupt levels from 0 to 3. These flags set the interrupt level for interrupt requests.

Figure 3-2-20 Serial Interface 1 Reception Interrupt Control Register (SC1ICR : x'03FF6', R/W)

III- 32 Control Registers