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Panasonic MN101C77C „ROM Correction Address 2 Setting Register RC2AP, Correspondence, RC2APH

Models: F77G MN101C77C

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Chapter 2 CPU Basics

ROM Correction Address 2 Setting Register (RC2AP)

7 6 5 4 3 2 1 0

RC2APL RC2APL7 RC2APL6 RC2APL5 RC2APL4 RC2APL3 RC2APL2 RC2APL1 RC2APL0 ( At reset : X X X X X X X X)

Figure 2-7-9 ROM Correction Address 2 Setting Register (lower 8 bits)

(RC2APL : x'03FCD', R/W)

7 6 5 4 3 2 1 0

RC2APM RC2APM7 RC2APM6RC2APM5RC2APM4RC2APM3RC2APM2RC2APM1RC2APM0 ( At reset : X X X X X X X X )

Figure 2-7-10 ROM Correction Address 2 Setting Register (middle 8 bits)

(RC2APM : x'03FCE', R/W)

RC2APH

7	6	5	4	3	2	1	0
-	-	-	-	-	-	RC2APH1	RC2APH0	( At reset : - - - - - -	X X )

Figure 2-7-11 ROM Correction Address 2 Setting Register (upper 2 bits)

(RC2APH : x'03FCF', R/W)

Do not set the same address to more than two RCnAP (H/M/L) register. If there are several registers set the same address, the order of priority is as follows :

RC0AP > RC1AP > RC2AP

Here is the correspondence of the ROM correction address setting register, a ROM correction control flag of ROM correction control register and the RC rector table.

	Table 2-7-1	Correspondence

ROM Correction address setting register			ROM correction	RC-vector table
			control flag
Register	Address		control flag	Vector	Address

RC0APL	x'3FC7'			RC0V(L)	x'0010'
			RC0EN
RC0APM	x'3FC8'
RC0APM	x'3FC8'			RC0V(H)	x'0012'

RC0APH	x'3FC9'
RC0APH	x'3FC9'

RC1APL	x'3FCA'			RC1V(L)	x'0014'
			RC1EN
RC1APM	x'3FCB'
RC1APM	x'3FCB'			RC1V(H)	x'0011'

RC1APH	x'3FCC'
RC1APH	x'3FCC'

RC2APL	x'3FCD'			RC2V(L)	x'0013'
			RC2EN
RC2APM	x'3FCE'
RC2APM	x'3FCE'			RC2V(H)	x'0015'

RC2APH	x'3FCF'
RC2APH	x'3FCF'

II- 34 ROM Correction

Image 86

Panasonic MN101C77C, F77G user manual „ROM Correction Address 2 Setting Register RC2AP, Correspondence, RC2APH

Contents

MN101C77C/F77G LSI User’s Manual Page Page Main text Key information Precautions and warningsSubtitle Sub-subtitle Summary„Finding Desired Information Page Page Contents Chapter Chapter Ports Chapter Prescaler Chapter Bit Timer Chapter Watchdog Timer Serial Interface Automatic Transfer Controller Chapter Appendices 18-4 Reprogramming Flow Page Chapter Overview Product Summary OverviewOverview Product SummaryKB Flash version 128 KB Hardware FunctionsCPU Core MN101C Core KB Flash version 6 KBTimer 1 8-Bit timer for general use Timers Timers 6 can operate independentlyTimer 0 8-Bit timer for general use External interrupts with/without noise filter‰ Time base timer Timer 4 8-Bit timer for general use or Uart baud rate timerTimer 5 8-Bit timer for general use or Uart baud rate timer Timer 7 16-Bit timer for general useFull-Duplex Uart Baud rate timer Timer Watchdog timerRemote control output Buzzer output‰ Single master IIC LED driver Pins Port PortsSpecial pins Pins Serial interface 4 Slave IIC ‰ IIC slave serial interfaceOverview Pin Configuration Pin DescriptionPin Specification Pin Functions 3 Pin Function Summary 1/64 Pin Function Summary 2/6 5 Pin Function Summary 3/6 6 Pin Function Summary 4/6 7 Pin Function Summary 5/6 8 Pin Function Summary 6/6 KEY1Block Diagram Block DiagramTo Vss Electrical CharacteristicsAbsolute Maximum Ratings *2,*3 voltages referenced 1 Crystal Oscillator MIN TYPClock duty rate should be 45% to 55% MIN TYP MAXTwh1 Twl1 Twr1 Twf1 Twc1 Twh2 Twl2 Twr2 Twf2 Twc2Characteristics 5 AC Zero-Cross Detector VDD=3.3 V,V IN=V SS Pin 7 P80 to P87 Input high voltage Converter Characteristics *2 LSBResolution *1 Bits Reference voltage low level Precautions General UsageUnused Pins 1 Unused Pins only for input3 Unused I/O pins high impedance output at reset Power Supply Reset Input Voltage Reset pin low level TimePower Supply Circuit 6 An Example for Emitter follower type Power Supply CircuitPackage Dimension Package Code LQFP064-P-1414Package Code TQFP064-P-1010C Chapter CPU Basics CPU Basics 1 Block Diagram and Function Readable / Writable Part of bit is only readable CPU Control Registers2 CPU Control Registers 2 Instruction Execution Controller Configuration Instruction Execution ControllerPipeline Process Registers for AddressDW1 Registers for DataDW0 Processor Status Word 3 Processor Status WordPSW3 Interrupt Mask Level and Interrupt Acceptance Addressing Modes 4 Addressing Modes PSWMemory Space Memory Mode1 Memory Mode Setup Single-chip Mode 2. Internal ROM / Internal RAMSpecial Function Registers 3 Register MapBus Interface Bus ControllerControl Registers 2 Memory Control Register Memctr x03F01 R/W„Memory Area Control Register Areactr 3 Memory Area Control Register Areactr x03F03, R/W„Bus Mode Control Register CSMDn 4 Bus Mode Control Register CSMDn x03F05 to x03F09, R/WStandby Function 1 Transition Between Operation ModesII 20 Standby Functions CPU Mode Control Register 2 Operating Mode and Clock Oscillation Cpum x3F00, R/WTransition between Slow and Normal Transition to Standby Modes Processing inside parentheses is handled by hardwareNOP Clock Switching OscmdCPU Address Range Bank SettingBank Function Bank area Address range DBA1 DBA0Dbnkr „Bank Register for Source AddressSbnkr „Single Chip Mode Bank Memory SpaceROM Correction Correction SequenceROM Correction ROM Correction Control Register Rcctr„ROM Correction Address 1 Setting Register RC1AP RC2APH „ROM Correction Address 2 Setting Register RC2APCorrespondence ROM Correction Setup Example 12 Initial Routine for ROM Correction06BB FF RC0VL, RC0VHRC0VL = xB4 RC0VH = RC1VH = Corrected at second to the ROM correction addressRC1VL = xBC Reset Reset operation2 Reset Released Sequence Dlyctr Oscillation Stabilization Wait timeNrst Stop Wdctr„Oscillation Stabilization Wait Time Control Register Register Protection Setting of the Register Protection FunctionRewrite Procedure Loop MOVChapter Interrupts III 2 Overview Functions Interrupt FunctionsPSW CPU coreOperation RTI2 Interrupt Vector Address and Interrupt Group 3 Interrupt Priority Outline Level judgement. Accepted if Ilim Generated interrupt level ILInterrupts PC bits 8-1 → SP+1 Contents of the PSW are saved to the stackPC bits 16-9 → SP+2 PSW →Maskable Interrupt 6 Processing Sequence for Maskable InterruptsIII 12 Overview 7 Processing Sequence with Multiple Interrupts Enabled Interrupt flag setup procedure Interrupt Flag SetupInterrupt request flag IR setup by the software 1 Interrupt Control Registers Control RegistersRegisters List Interrupt Control Registers 1 Non-Maskable Interrupt Control Register NMICRx03FE1, R/WIRQ0ICR REDG0 IRQ0IE IRQ0IR LV13 External Interrupt 1 Control Register IRQ1ICR x03FE3, R/W IRQ2ICR REDG2 IRQ2IE IRQ2IR IRQ2 LV1 LV05 External Interrupt 3 Control Register IRQ3ICR x03FE5, R/W IRQ3ICR REDG3 IRQ3IE IRQ3IR6 External Interrupt 4 Control Register IRQ4ICR x03FE6, R/W IRQ4ICR REDG4 IRQ4IE IRQ4IRTM0ICR TM0IE TM0IR LV1 TM0TM1ICR TM1IE TM1IR LV1 TM1TM4ICR TM4IE TM4IR LV1 TM4TM5ICR TM5IE TM5IR TM5TM6ICR TM6IE TM6IR LV1 TM615 Time Base Interrupt Control Register Tbicr x03FF0, R/W Tbicr Tbie Tbir LV1TM7ICR TM7IE TM7IR LV1 TM7T7OC2IR T7OC2IESC0RIR SC0RIE SC0R SC0R LV1 LV0SC0TIR SC0TIE SC0T SC0T LV1 LV0SC1RIR SC1RIE SC1R SC1R LV1 LV0SC1TIR SC1TIE SC1T SC1T LV1 LV0SC3ICR SC3IE SC3IR LV1 LV0 SC3SC4ICR SC4IE SC4IR LV1 LV0 SC4Adicr Adie Adir ATC1 ATC1IRATC1IE External Interrupts 1 External Interrupt FunctionsExternal Interrupts P23/IRQ3 Noise filter3 Polarity Inversion Edge detection External Interrupt 4 Interface Block Diagram 3 External Interrupt 4 Interface Block Diagram2 External Interrupt Control Register Readable / WritableNF1EN NFCTR0 P21IMNF0EN 5 Noise Filter Control Register 1 NFCTR1 x03F8D, R/W 6 Both Edges Interrupt Control Register Edgdt x03F8F, R/W Port 6 Key Interrupt Control Register P6IMD 7 Port 6 Key Interrupt Control Register P6IMD x03F3E, R/WRising edge as the active edge for interrupts Programmable Active Edge InterruptREDG4 IRQ4IEBoth Edges Interrupt IRQ2IEKey Input Interrupt IRQ4SEL External interrupt 4 source to the port 6 key4 Sampling Cycle / Time of Noise Remove Function Noise Filter3 Noise Remove Function 8 Noise Remove Function Operation NF0EN REDG0Interrupt active edge to the rising edge IRQ0IEAC Zero-Cross Detector 9 AC Line Waveform and IRQ1 Generation TimingIRQ1IE Page Chapter Ports 1 I/O Port Diagram 1 I/O Port FunctionsPort Status at Reset 1 I/O Port Status at Reset Single chip mode2 I/O Port Control Registers List 1/2 3 I/O Port Control Registers List 2/2 Port DescriptionRegisters P0IN P0DIR2 Block diagram P00 4 Block diagram P02 6 Block Diagram P04 8 Block Diagram P06 IV 12 Port Port 1 input register P1IN x03F21, R Port 1 output mode register P1OMD X03F2F, R/W P10 Output Control register P1TCNT X03F7E, R/W 4 Block Diagram P10, P12, P14 Port 2 IV Port 2 input registerP2IN x02F22, R 2 Block Diagram P20, P22 to P24 4 Block Diagram P27 Port 5 IV Port 5 input register P5IN x03F25, R 2 Block Diagram P50 4 Block Diagram P52 6 Block Diagram P54 IV 26 Port Port 6 output register P6OUT x03F16, R/W Port 6 Synchronous Output Control Register P6SYOX03F1E, R/W 3 Block Diagram P60 to P67 IV 30 Port Port 7 output register P7OUT x03F17, R/W 2 Port 7 Registers 2/2 Block Diagram P70 5 Block Diagram P72 7 Block Diagram P74 9 Block Diagram P76, P77 8Port Port 8 output register P8OUT x03F18, R/W Port 8 LED Control register P8LED x03F1D, R/W 3 Block Diagram P80 to P87 9Port a Port a output register Paout X03F1A, R/W Port a Input control register Paimd X03F3C, R/W 3 Block Diagram PA0 to PA1 10-1 Real Time Output Control Registers Real Time Output Control Port10-1 shows the real time output control register of port IV 46 Real Time Output Control Port 10-1 Real Time Output Control Timing 11-1 Synchronous Output Control Block Diagram Synchronous output Port11-1 shows the synchronous output control registers of port 11-1 Synchronous Output Control Registers11-2 Synchronous Output Event 11-2 Synchronous Output Timing by Event Generation IRQ2 Setup Example IRQ2Chapter Prescaler Prescaler Peripheral Functions 1 Peripheral Functions Used with Prescaler OutputBlock Diagram 1 Prescaler Control Registers Control Register1 shows registers to control prescaler 1 Prescaler Control Register Pscmd x03F6F, R/W 2 Timer 0 Prescaler Selection Register CK0MD x03F56, R/W „Timer 1 prescaler selection register CK1MD„Timer 4 Prescaler Selection Register CK4MD „Timer 5 Prescaler Selection Register CK5MD„Serial Interface 1 Transfer Clock Selection Register SC1CKS „Serial Interface 3 Transfer Clock Selection Register SC3CKS CK1MD OperationCK0MD CK4MDPscmd to TM0BASPscen Chapter Bit Timers Functions 1 shows functions of each timer1 Timer Functions TM0IRQ TM1IRQ TM4IRQ TM5IRQ„Timers TM1MDDiagram „TimerBlock Diagram Rmctr „Remote Control Carrier Output Block DiagramMUX 1 8-bit Timer Control Registers TM4BC „Timer 4 Compare Register TM4OC Programmable Timer Registers„Timer 1 Compare Register TM1OC „Timer 5 Compare Register TM5OC„Timer 5 Binary Counter TM5BC „Timer 1 Binary Counter TM1BC„Timer 4 Binary Counter TM4BC TM0EN Timer Mode RegistersTM0MD TM0PWMTM1EN „Timer 1 Mode Register TM1MDTM1MD TM1CASTM4EN „Timer 4 Mode Register TM4MDTM4MD TM4MODTM5EN „Timer 5 Mode Register TM5MDTM5MD TM5MOD„Remote Control Carrier Output Control Register Rmctr Rmbtms8-bit Timer Count 1 Clock Source Timers 0, 1, 4 and 5 at Timer Operation1 Count Timing of Timer Operation Timers 0, 1, 4 TM0MOD TM0ENTM0PWM TM0IE 8-bit Event Count 1 Event Count Input Clock2 Count Timing of Synchronous TMnIO Input Timers 0, 1, 4 P1DIR1 TM0ICRVI 22 8-bit Event Count „Count Timing of Timer Pulse Output Timers 0, 1, 4 8-bit Timer Pulse Output1 Timer Pulse Output Pins P1OMD0 P1DIR0Bit Timers 8-bit PWM Output 1 Output Pins of PWM Output„Count Timing of PWM Output at normal Timers 0, 4 2 Count Timing of PWM Output when compare register is P1DIR x3F31 Control register P1DIR to 1 for the output Bp0 PWM operationTM0EN „Count Timing of Synchronous Output Timer 1, Timer 8-bit Timer Synchronous Output1 Synchronous Output Port Timer 1, Timer TM1BAS TM1ENTM1CAS Pscmd x3F6F Prescaler counting Bp0VI 32 Synchronous Output Serial Interface Transfer Clock Output 1 Timer for Serial Interface Transfer Clock„Timing of Serial Interface Transfer Clock Timers 4 TM4MOD TM4ENTM4PWM TM4BASBit Timers 1 Simple Pulse Width Measurement Able Pins Timers 0, 4 Simple Pulse Width MeasurementIRQ2ICR REDG2VI 38 Simple Pulse Width Measurement 10-1 Timer Functions at Cascade Connection Cascade ConnectionVI 40 Cascade Connection Connection Timer 1 mode register to 0 to stop timer 0TM1MD x3F55 Timer 1 counting Bp3 TM1IE Remote Control Carrier Output 11-1 Duty Cycle of Remote Control Carrier Output SignalRMDTY0 RmoenRmbtms TM0RMNormal timer operation Page Chapter Bit Timer 1 shows the functions of timer 1 16-bit Timer Functions1 Timer 7 Block Diagram „Timer 7 Block DiagramReadable/Writable Readable only 1 shows the registers that control timer1 16-bit Timer Control Registers 1 Timer 7 Compare Register 1 Lower 8 bits TM7OC1L x03F72, R „Timer 7 Compare Register 2 TM7OC25 Timer 7 Preset Register 1 Lower 8 bits TM7PR1L x03F74, R/W „Timer 7 Preset Register 2 TM7PR29 Timer 7 Binary Counter Lower 8 bits TM7BCL x03F70, R TM7CL TM7CK0TM7EN „Timer 7 Mode Register 2 TM7MD2 16-bit Timer Count 2 Clock Source at Timer OperationTimer 2 shows the clock source that can be selectedVII 12 16-bit Timer Count Compare match as a binary counter clear TM7ENTM7BCR TM7IEVII 14 16-bit Timer Count 1 Count Timing TM7IO Input Timer 16-bit Event Count2 Count Timing of Synchronous TM7IO Input Timer Compare match as a clear source of binary CounterVII 18 16-bit Event Count 16-bit Timer Pulse Output 1 Timer Pulse Output Pin„Count Timing of Timer Pulse Output Timer 1 Count Timing of Timer Pulse Output TimerSource of a binary counter TM7PWMPulse output TM7CL 1 PWM Output Pin „Count Timing of Standard PWM Output at NormalTimer16-bit Standard PWM Output PWM output shows H , when TM7EN flag is stopped at 4 Output Waveform of TM7IO Output Pin VII 26 16-bit Standard PWM Output 16-bit High Precision PWM Output Cycle/Duty can be changed consecutivelyVII 28 16-bit High Precision PWM Output P1OMD4 Also, set the T7PWMSL flag to 1 to selectVII 30 16-bit High Precision PWM Output 16-bit Timer Synchronous Output 1 Count Timing of Synchronous Output TimerSource of the binary counter TM7EN 16-bit Timer Capture Capture Trigger3-4. Programmable active Edge Interrupt VII 36 16-bit Timer Capture External interrupt IRQ 0 input Pulse width to be measured 3 Pulse Width Measurement of External InterruptT7ICEDG T7ICENChapter Time Base Timer Bit Free-running Timer 1 Clock Source and Generation Cycle Tbirq TM6IRQ„Timer 6, Time Base Timer Block Diagram 1 Block Diagram Timer 6, Time Base Timer1 shows the registers that control timer 6, time base timer Control RegistersTM6OC „Timer 6 Compare Register TM6OCTM6BC TbclrTM6CLRS TM6MDTM6CKS0 8-bit Free-running Timer 1 Clock Source at Timer Operation TimerBp1 Hz1 s 2 1 minute-timer, 1 second-timer Setup TimerTM6BC 2 Count Timing of Timer Operation Timer Set the TM6IE flag of the TM6ICR register to TM6ICR x3FEF Bp1TM6IE Above steps 1, 2 can be set at onceViii Time Base Timer 1 Time Base Timer Interrupt Generation Cycle1 Count Timing of Timer Operation Time Base Timer Tbie TbicrIf the interrupt request flag had already been Chapter Watchdog Timer „Watchdog Timer Block Diagram 1 Block Diagram Watchdog Timer1 Watchdog Timer Control Register Wdctr x03F02, R/W Watchdog timer cannot stop, once it starts operation 1 Watchdog Timer Period 2 The Lowest Value for Watchdog Timer ClearIX 6 Operation Setup Example Maskable interrupt control register Nmicr is On the interrupt service routine,Tbnz Nmicr WDIR, Wdpro Manage the suitable executionBuzzer „Buzzer Block Diagram 1 Block Diagram Buzzer„Oscillation Stabilization Wait Timer Control Register 1 Buzzer Output Frequency BUZS2 BUZS1 BUZS0Operation X Page Serial Interface 0,1 1 Serial Interface 0, 1 used pins P01/SBI1A/RXD1A P74/SBI1B/RXD1B P02/SBT1A P75/SBT1B1 shows functions of serial interface 0 1 Serial Interface 0, 1 Functions1 Serial Interface 0 Block Diagram „Serial Interface 0 Block Diagram2 Serial Interface 1 Block Diagram „Serial Interface 1 Block DiagramReadable / Writable Readable only 1 shows registers to control serial interface 01 Serial Interface 0, 1 Control Registers Serial Interface 0 Data Buffer Registers „Serial Interface 0 Transmissin Data Buffer TXBUF0Serial Interface 0 Mode Registers „Serial Interface 0 Mode Register 0 SC0MD0„Serial Interface 0 Mode Register 1 SC0MD1 4 Serial Interface 0 Mode Register 1 SC0MD1 x03F93, R/W„Serial Interface 0 Mode Register 2 SC0MD2 SC0BRKF flag is only for reading„Serial Interface 0 Mode Register 3 SC0MD3 All flags are only for reading„Serial Interface 0 Port Control Register SC0ODC „Serial Interface 0 Transfer Clock Selection Register SC0CKS Serial Interface 1 Data Buffer Registers „Serial Interface 1 Transmissin Data Buffer TXBUF1Serial Interface 1 Mode Registers „Serial Interface1 Mode Register 0 SC1MD0„Serial Interface 1 Mode Register 1 SC1MD1 12 Serial Interface 1 Mode Register 1 SC1MD1 x03F9B, R/W„Serial Interface 1 Mode Register 2 SC1MD2 SC1BRKF flag is only for reading„Serial Interface 1 Mode Register 3 SC1MD3 14 Serial Interface 1 Mode Register 3 SC1MD3 x03F9D, R„Serial Interface 1 Port Control Register SC1ODC „Serial Interface1 Transfer Clock Selection Register SC1CKS SC1CKSClock Synchronous Serial Interface 1 Synchronous Serial Interface Activation FactorXI 22 Operation TXBUFn 2 Transmission Data Output Edge and Received Data Input Edge 3 Synchronous Serial Interface Internal Clock Source XI 26 Operation 4 Last Bit Data Length of Transfer Data 5 Other Control Flag„Trasnmission Timing Tmax=1.5 T Tmax=2 T 9 Reception Timing rising edge, start condition is enabled „Reception Timing11 Reception Timing falling edge, start condition is enabled XI 32 Operation Serial interface 0 Synchronous Serial Interface Pin Setup XI 34 Operation P7DIR P7DIR0 P7DIR P7DIR7 Serial interface 1 Synchronous Serial Interface Pin Setup SC0ODC SC1SEL XI 38 Operation MSB XI 40 Operation Interrupt Flag Setup Uart Serial Interface 17 Uart Serial Interface FunctionsSerial Interface 0 15 shows the data format at Uart communication 18 Uart Serial Interface Transmission / Reception Data19 Uart Serial Interface Frame Mode 20 Parity Bit of Uart Serial Interface21 Reception Error Source of Uart Serial Interface Serial Interface 0 XI 48 Operation 16 Transmission Timing parity bit is enabled „Transmission Timing18 Reception Timing parity bit is enabled 22 Uart Serial Interface Transfer Rate Setup Register 23 Uart Serial Interface Transfer Rate Setup Register24-1 Uart Serial Interface Transfer Rate decimal 9600 19200 28800 31250 38400 MHz Timer 24-2 Uart Serial Interface Transfer Rate decimalSerial interface 0 Uart Serial Interface Pin Setup SC0ODC SC0SEL27 Uart Serial Interface 0 Pin Setup 1 channel, at reception Serial interface 1 Uart Serial Interface Pin Setup SC1ODC SC1SEL31 Uart Serial Interface 1 Pin Setup 1 channel, at reception 33 Uart Interface Transmision Reception Setup Serial Interface 0 XI 60 Operation Serial Interface 1 shows the functions of serial interface 1 Serial Interface 3 Functions List12-1-2 Block Diagram 1 shows the registers to control serial interface 1 Serial Interface 3 Control RegistersData Register SC3TRBMode Registers „Serial Interface 3 Mode Register 0 SC3MD0„Serial Interface 3 Mode Register 1 SC3MD1 3 Serial Interface 3 Mode Register 1 SC3MD1 x03FA9, R/W„Serial Interface 3 Control Register SC3CTR „Serial Interface 3 Port Control Register SC3ODC 1 Activation factor of Synchronous Serial Interface 1-1 Transfer Bit Count and First Transfer Bit at MSB first „Receive Bit Count and First Transfer Bit2 Synchronous Serial Interface Internal Clock Source 3 Input Edge/Output Edge of Transmission/Received Data 4 Last Bit Data Length of Transmission Data2 Transmission Timing Falling edge, Enable Start Condition 4 Transmission Timing Rising edge, Enable Start Condition 6 Reception Timing Rising edge, Enable Start Condition 8 Reception Timing Falling edge, Enable Start Condition XII 18 Operation SBI3/SBO3 XII 20 Operation SC3ODCSC3ODC0 SC3ODCSC3ODC1 P5PLUP5PLU1 P5PLUP5PLU2XII 22 Operation Function Port Serial data input Serial clock I/O XII 24 Operation Interrupt Flag Setup XII 26 Operation Single Master IIC Interface 11 IIC Serial Interface Functions12 Start Condition and Stop Condition 13 ACK Bit Reception Timing after Transmission of 8-Bit Data Free data format master transmission Addressing format master transmissionAddressing format master reception 12 IIC Interface Clock Source16 Master Transmission Timing, -3-17 Master Reception Timing „Master Transmission Timing 16 Master Transmission Timing„Master Reception Timing 17 Master Reception Timing13 Pin Setup 2 channels, at transmission 14 Pin Setup 2 channels, at reception 15 Conditions Single Master IIC Communication Setup Serial Interface XII 38 Operation Is . When SC3ACKO = 1, the reception at XII 40 Operation Serial Interface 1 Serial interface 4 Functions List „Serial interface 4 Block Diagram SC4STR1 Serial interface 4 Control Registers 1 Serial interface 4 Reception Data Buffer SC4RXB x03FAD, R „Serial interface 4 Transmission Data Buffer SC4TXBI2CAD7 I2CAD6 I2CAD5 I2CAD4 I2CAD3 I2CAD2 I2CAD1 I2CAD0 „Serial interface 4 Addressing Register 0 SC4AD0„Serial interface 4 Addressing Register 1 SC4AD1 „Serial interface 4 Status Register SC4STR 5 Serial interface 4 Status Register SC4STR x03FAC, R„Serial interface 4 Port Control Register 0 SC4ODC0 „Serial interface 4 Port Control Register 1 SC4ODC1Operation Xiii SC4ODC1 Pin SetupSC4ODC0 Setup Example of the Slave IIC Serial Interface Xiii 12 Operation Automatic Transfer Controller 14-1-1 ATC1 Transfer Modes 1 ATC1 Trigger Factors„ATC Transfer Modes „ATC1 Block Diagram 1 ATC1 Block Diagram1 shows the registers used to control ATC1 1 ATC1 Control Registers„ATC1 Control Register 0 AT1CNT0 1 ATC1 Control Register 0 AT1CNT0 x03FD0, R/W„ATC1 Control Register 1 AT1CNT1 „ATC1 Transfer Counter AT1TRC„ATC1 Memory Pointer 0 AT1MAP0 „ATC1 Memory Pointer 1 AT1MAP1Basic Operations and Timing „Data transfer „Transfer end„Memory pointer 0 functions Setting the Memory Address„Setting the transfer addresses to the memory pointers „Memory pointer 1 functions„The transfer data counter AT1TRC Setting the Data Transfer Count„Transfer data counter AT1TRC function „Standard and burst transfers Setting the Data Transfer Modes„Data transfer modes AT1MAP1 Transfer ModeAT1MAP0 3 Transfer Mode 4 Transfer Mode 5 Transfer Mode 6 Transfer Mode 7 Transfer Mode 8 Transfer Mode Automatic Transfer Controller 9 Transfer Mode Automatic Transfer Controller 10 Transfer Mode Automatic Transfer Controller 11 Transfer Mode Automatic Transfer Controller Transfer mode a 12 Transfer Mode aTransfer Mode B 13 Transfer Mode BTransfer Mode C 14 Transfer Mode CTransfer Mode D 15 Transfer Mode DTransfer Mode E 16 Transfer Mode ETransfer Mode F 17 Transfer Mode FAT1ACT Setup ExampleFmode AT1ENSetup Example Page Converter 1 shows the A/D converter functions 1 A/D Converter FunctionsHold 1 shows the registers used to control A/D converter 1 A/D Converter Control RegistersAnlade „A/D Converter Control Register 0 ANCTR0ANCTR0 ANSH1 ANCTR2 Anst „A/D Converter Control Register 1 ANCTR1„A/D Converter Control Register 2 ANCTR2 AnstselData Buffers ANBUF1XV 8 Operation 1 Operation of A/D Conversion 2 A/D Conversion Clock and A/D Conversion Cycle Setup1 Input Pins of A/D Converter Setup 3 Sampling Time of A/D Conversion and A/D Conversion Time6 A/D Conversion Starting 4 A/D Ladder Resistor Control5 A/D Conversion Activation Factor Selection 4 Interrupt Flag Setting Converter Padir Converter 2 A/D Converter Recommended Example Recommended Connection with A/D Converter Page Converter 1 shows the D/A converter functions 1 D/A Converter FunctionsOperation XVI 1 D/A Converter Control Registers Readable/WritableControl Register Dactr 1 D/A Converter Control Register Dactr x03FBE R/WInput Data Registers 2 D/A Converter Input Data Register 01 DADR01 x03FBF R/WPaplud Page Appendices Top view of MBB board Probe SwitchesPRB-MBB101C77-M OFF OP0 OP1 OP2 OP3 OP4 OP5PX-CN101-M MBB board PRB-MBB101∗∗∗-MPRB-ADP101-64-M MBB board PRB-MBB101∗∗∗-M17-1-4PRB-DMY101C77-M MBB board PRB-MBB101C77-M17-2 Special Function Registers List Special Function Registers List Xvii 8 Special Function Registers List TM1OC2 Xvii 10 Special Function Registers List SC0ODC Xvii 12 Special Function Registers List Nmicr Xvii 14 Special Function Registers List I2CAD7 I2CAD6 I2CAD5 I2CAD4 I2CAD3 I2CAD2 I2CAD1 I2CAD0 Instruction Set MOVInstruction Set D4 sign-extension D7 sign-extension D11 sign-extension Cbeq JMP INC ADD DEC Addw INC2 DEC2 CLR SUB 17-4 Instruction MapVer2.12001.03.26 Page Flash Eeprom Eeprom XVIII-2 Overview1 Memory Map in Internal Flash Eeprom Differences between Mask ROM version and Eprom version 1 Differences between Mask ROM version and Eprom version1 Pin Configuration LQFP064-P-1414 Pin DescriptionsAbsolute Maximum Ratings*2,*3 SensNormal mode fs=fosc/2, Slow mode fs=fx/2 Operating ConditionsDC Characteristics Reprogramming Flow 1 Reprogramming Flow of Internal Flash EepromProm writer mode „Pin Configuration for Socket Adaptor 2 Pin Configuration for Socket AdaptorOnboard Serial Programming Mode 1 Target Board for programming using the YDC Serial Writer This section describes each memory space of Flash Eeprom X06088 to X23FFF This area stores the user programXVIII-15 3 Target Board for programming using the PanaX Serial Writer Pull-up resistor value Maximum output current of pin I OLPull-up resistor RupMin X Load capacity MN101C77C/F77G Sales Offices