Panasonic MN101C77C, F77G user manual CPU Basics

Table 2-1-1 Basic Specifications

Chapter 2 CPU Basics

2-1 Overview

The MN101C CPU has a flexible optimized hardware configuration. It is a high speed CPU with a simple and efficient instruction set. Specific features are as follows:

1. Minimized code sizes with instruction lengths based on 4-bit increments

The series keeps code sizes down by adopting a basic instruction length of one byte and variable instruction lengths based on 4-bit increments.

2.Minimum execution instruction time is one system clock cycle.

3.Minimized register set that simplifies the architecture and supports C language

The instruction set has been determined, depending on the size and capacity of hardware, after an analysis of embedded application programing code and creation code by C language compiler. Therefore, the set is simple instruction using the minimal register set required for C language

compiler. [ "MN101C LSI User's Manual" (Architecture Instructions) ]

	Load / store architecture
	Six registers	Data : 8-bit x 4
		Address : 16-bit x 2
Structure
		PC : 19-bit
	Other	PSW : 8-bit
		SP : 16-bit
	Number of instructions	37
	Addressing modes	9
Instructions
		Basic portion : 1 byte (min.)
	Instruction length	Extended portion : 0.5-byte x n
		(0 < n < 9)
	Instruction execution	Min. 1 cycle
Basic performance	Inter-register operation	Min. 2 cycles
	Load / store	Min. 2 cycles
	Conditional branch	2 to 3 cycles
Pipeline	3-stage (instruction fetch, decode, execution)
Address space	256 KB (max. 64 KB for data)
	Address	18-bit (max.)
External bus
	Data	8-bit
	Minimum bus cycle	1 system clock cycle
Interrupt	Vector interrupt	3 interrupt levels
Low-power	STOP mode
dissipation mode	HALT mode

II - 2 Overview