Panasonic F77G, MN101C77C user manual Clock Switching, Oscmd

Chapter 2 CPU Basics

2-5 Clock Switching

This LSI can select the best operation clock for system by switching clock cycle division factor by program. Division factor is determined by both flags of the CPU mode control register (CPUM) and the Oscillator frequency control register (OSCMD). At the highest-frequency, CPU can be operated in the same clock cycle to the external clock hence providing wider operating frequency range.

OSCMD

7	6	5	4	3	2	1	0
-	-	-	-	-	-	SOSC2DS	Reserved

( At reset : - - - - - - 0 0 )

Reserved	Set "0", always.
SOSC2DS	Low-frequency Clock

0Standard (Input the oscillation clock cycle)

1Divided (Input the oscillation clock cycle divided by 2)

Figure 2-5-1 Oscillator Frequency Control Register (OSCMD : x'03F2D', R/W)

CPUM

7	6	5	4	3	2	1	0
SOSCDBL	OSCSEL1	OSCSEL0	OSCDBL	STOP	HALT	OSC1	OSC0

( At reset : 0 0 0 0 0 0 0 0 )

OSCDBL	Internal System Clock
0	Standard (Input the oscillation clock cycle
	divided by 2)
1	2x-speed (Input the oscillation clock cycle)
OSCSEL1	OSCSEL0	Division factor
		NORMAL mode	SLOW mode
0	0	1	1
0	1	4	4
1	0	16	16
1	1	64	16

SOSCDBL	Low Speed Oscillation Clock
0	Standard (Input the oscillation clock cycle
	divided by 2)
1	2x-speed (Input the oscillation clock cycle)

Figure 2-5-2 CPU Mode Control Register (CPUM : x'03F00', R/W)

Clock Switching II - 25