Panasonic MN101C77C, F77G user manual Control Registers, Memory Control Register Memctr x03F01 R/W

Chapter 2 CPU Basics

2-3-2 Control Registers

Bus interface is controlled by these 8 bytes of registers : the memory control register (MEMCTR), memory area control register (AREACTR) and bus mode control register (CSMDn).

„Memory Control Register (MEMCTR)

MEMCTR

7 6 5 4 3 2 1 0

IOW1	IOW0	IVBM EXMEM EXWH IRWE	EXW1 EXW0	( At reset : 1 1 0 0 1 0 1 1 )
				EXW1 to 0	Fixed wait cycles	Bus cycle at
						20 MHz oscillation
				0 0	No wait cycles	100 ns
				0 1	1 wait cycle Don't care 150 ns
				1 0	2 wait cycles	200 ns
				1 1	3 wait cycles	250 ns
				IRWE	Software write enable flag for interrupt request flag
					Software write disable
				0	Even if data is written to each interrupt control
					register (xxxICR), the state of the interrupt
					request flag (xxxIR) will not change.
				1	Software write enable
				EXWH	Fixed wait cycle mode or handshake mode
				0	Handshake mode
					Don't care
				1	Fixed wait cycle mode
				EXMEM	Set always to "0"
				IVBM	Base address setting for interrupt vector table
				0	Interrupt vector base = x'04000'
				1	Interrupt vector base = x'00100'
				IOW1 to 0	Wait cycles when	Bus cycle at
					accessing special register area	20 MHz oscillation

0 0	No wait cycles		100 ns
0 1	1 wait cycle	Don't care150 ns
1 0	2 wait cycles
			200 ns
1 1	3 wait cycles		250 ns

Figure 2-3-2 Memory Control Register (MEMCTR: x'03F01' R/W)

EXW1 to 0, EXWH and IOW1 to 0 flags of the memory control register (MEMCTR) need not to be set. Set wait cycle with bus mode control register (CSMDn).

II- 16 Bus Interface