2.4 System Board Troubleshooting | 2 Troubleshooting Procedures |
Table
D port status | Inspection items | Details |
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F100H | IRT_START |
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| Process of cache control for |
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| HyperThreading |
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| Prohibition of cache |
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| Initialization of H/W (before DRAM | Initialization of MCHM |
| recognition) |
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| Initialization of ICH4M.D31.Func0 | |
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| Initialization of ICH4M.D31.Func1 |
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| Initialization of USB.Func0,1,2,7 |
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| Initialization of ICH4M.D31.Func3 |
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| Initialization of ICH4M.D31.Func5 |
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| Initialization of FLUTE |
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| Initialization of PIT channel 1 | (Setting the refresh interval to “30μs”) |
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F101H | IRT_INI_SPREG_END |
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| Check of DRAM type and size | When unsupported memory is connected, |
| (at cold boot) | becoming HLT after beep sound (HLT when |
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| DRAM size is 0) |
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| HLT When it can not be used as a stack | |
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F102H | Cache configuration |
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| Cache permission (L1/L2 Cache) |
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| CMOS access test (at cold boot) | (HLT when an error is detected) |
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| Battery level check of CMOS |
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| CMOS checksum check |
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| Initialization of CMOS data (1) |
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| Setting of IRT status | (Setting of boot status and IRT busy flag, The rest |
| bits are 0) | |
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| |
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| Storing DRAM size in CMOS |
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| Cache configuration |
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F103H | IRT_RSM_BRANCH |
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| Resume branch (at cold boot) | Not resume when a CMOS error occurred |
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| Not resume when resume status code is not set |
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| Resume error check |
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| S3 returning error (ICH) |
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| Resume error F170 RSM_UNKNOWN_ERR |
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PORTÉGÉ M500 Maintenance Manual | [CONFIDENTIAL] |
