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IBM 750GL Manual

IBM 750GL Manual

377 pages3.48 Mb

3List of Figures
List of Tables
About This Manual
53. Instruction-Cacheand Data-CacheOperation
4. Exceptions
76. Instruction Timing
98. Bus Interface Operation
1010. Power and Thermal Management
11. Performance Monitor and System Related Features
11Acronyms and Abbreviations
Index
Revision Log
13List of Figures
15List of Tables
19About This Manual
- Who Should Read This Manual
- Related Publications
- 20Conventions Used in This Manual
- 21Terminology Conventions
- Instruction Field Conventions
- 22Using This Manual with the Programming Environments Manual
231. PowerPC 750GX Overview
- 1.1 750GX Microprocessor Overview
- 251.2 750GX Microprocessor Features
- 291.2.1 Instruction Flow
- 1.2.1.1 Instruction Queue and Dispatch Unit
- 1.2.1.2 Branch Processing Unit (BPU)
- 30bclr
- 1.2.1.3 Completion Unit
- 311.2.2 Independent Execution Units
- 1.2.2.1 Integer Units (IUs)
- 1.2.2.2 Floating-PointUnit (FPU)
- 321.2.2.3 Load/Store Unit (LSU)
- 1.2.2.4 System Register Unit (SRU)
- 1.2.3 Memory Management Units (MMUs)
- 331.2.4 On-ChipLevel 1 Instruction and Data Caches
- 351.2.5 On-ChipLevel 2 Cache Implementation
- 1.2.6 System Interface/Bus Interface Unit (BIU)
- 371.2.7 Signals
- 38Note
- 1.2.8 Signal Configuration
- 401.3 750GX Microprocessor Implementation
- 421.4 PowerPC Registers and Programming Model
- 451.5 Instruction Set
- 471.6 On-ChipCache Implementation
- 481.7 Exception Model
- 491.7.2 750GX Microprocessor Exception Implementation
- 511.8 Memory Management
- 521.9 Instruction Timing
- 541.10 Power Management
- 551.11 Thermal Management
- 561.12 Performance Monitor
572. Programming Model
- 2.1 PowerPC 750GX Processor Register Set
- 59Implementation Note:
- User-level
- registers
- Implementation Note
- lscbx
- mtxer
- 60Supervisor-level
- 62-specific
- 642.1.2 PowerPC 750GX-SpecificRegisters
- 2.1.2.1 Instruction Address Breakpoint Register (IABR)
- 652.1.2.2 Hardware-Implementation-DependentRegister 0 (HID0)
- 702.1.2.3 Hardware-Implementation-DependentRegister 1 (HID1)
- 712.1.2.4 Hardware-Implementation-DependentRegister 2 (HID2)
- 722.1.2.5 Performance-MonitorRegisters
- 772.1.3 Instruction Cache Throttling Control Register (ICTC)
- 782.1.4 Thermal-ManagementRegisters (THRMn)
- 2.1.4.1 Thermal-ManagementRegisters 1–2 (THRM1–THRM2)
- 792.1.4.2 Thermal-ManagementRegister 3 (THRM3)
- 802.1.4.3 Thermal-ManagementRegister 4 (THRM4)
- 812.1.5 L2 Cache Control Register (L2CR)
- 822.2 Operand Conventions
- 832.2.3 Floating-PointOperand and Execution Models—UISA
- 2.2.3.1 Denormalized Number Support
- 2.2.3.2 Non-IEEEMode (Nondenormalized Mode)
- 842.2.3.3 Time-Critical Floating-PointOperation
- 2.2.3.4 Floating-PointStorage Access Alignment
- 2.2.3.5 Optional Floating-PointGraphics Instructions
- fsel(.)
- fres(.)
- frsqrte(.)
- 862.3 Instruction Set Summary
- 872.3.1 Classes of Instructions
- 2.3.1.1 Definition of Boundedly Undefined
- 2.3.1.2 Defined Instruction Class
- fsqrt
- fsqrts
- tlbia)
- 882.3.1.3 Illegal Instruction Class
- 892.3.1.4 Reserved Instruction Class
- 2.3.2 Addressing Modes
- 2.3.2.1 Memory Addressing
- 2.3.2.2 Memory Operands
- 902.3.2.3 Effective Address Calculation
- 2.3.2.4 Synchronization
- 91mfsrin)
- mtsrin
- 2.3.3 Instruction Set Overview
- 922.3.4 PowerPC UISA Instructions
- 2.3.4.1 Integer Instructions
- 93addi
- subf
- cmpi
- cmp
- cmpli
- cmpl
- 94andi
- andis
- 952.3.4.2 Floating-PointInstructions
- 96fmul
- fmadd
- fmsub
- fnmadd
- fnmsub
- frsp
- 98mtfsf
- 2.3.4.3 Load-and-StoreInstructions
- 100Implementation
- Notes
- lha
- lhax
- lbzu
- lbzux
- lhzu
- lhzux
- lhau
- lhaux
- lwu
- lwux
- lhbrx
- lbrx
- sthbrx
- stwbrx
- 102eieio)
- Implementation Notes:
- 104lfsx
- lfsux
- lfdx
- lfdux
- Programming Note:
- 106stfsu
- stfdu
- 2.3.4.4 Branch and Flow-ControlInstructions
- bla
- bca
- bcl
- bcla
- bclrl
- bcctrl
- crand
- cror
- crxor
- crnand
- crnor
- crandc
- creqv
- crorc
- 1082.3.4.5 System Linkage Instruction—UISA
- 2.3.4.6 Processor Control Instructions—UISA
- 109mtcrf
- 1132.3.4.7 Memory Synchronization Instructions—UISA
- 2.3.5 PowerPC VEA Instructions
- 2.3.5.1 Processor Control Instructions—VEA
- 114mftbu
- 2.3.5.2 Memory Synchronization Instructions—VEA
- 1152.3.5.3 Memory Control Instructions—VEA
- 1172.3.5.4 Optional External Control Instructions
- 1182.3.6 PowerPC OEA Instructions
- 2.3.6.1 System Linkage Instructions—OEA
- 2.3.6.2 Processor Control Instructions—OEA
- 1192.3.6.3 Memory Control Instructions—OEA
- 120tlbia
- 2.3.7 Recommended Simplified Mnemonics
1213. Instruction-Cacheand Data-CacheOperation
- 1233.1 Data-CacheOrganization
- 1243.2 Instruction-CacheOrganization
- 1253.3 Memory and Cache Coherency
- 126mtspr)
- 3.3.2 MEI Protocol
- 1283.3.2.1 MEI Hardware Considerations
- 1293.3.3 Coherency Precautions in Single-ProcessorSystems
- 3.3.4 Coherency Precautions in Multiprocessor Systems
- 1303.3.5 PowerPC 750GX-InitiatedLoad/Store Operations
- 3.3.5.1 Performed Loads and Stores
- 3.3.5.2 Sequential Consistency of Memory Accesses
- 3.3.5.3 Atomic Memory References
- 1313.4 Cache Control
- 1323.4.1.1 Data-CacheFlash Invalidation
- 3.4.1.2 Enabling and Disabling the Data Cache
- dcbz)
- dcbf)
- 3.4.1.3 Locking the Data Cache
- 1333.4.1.4 Instruction-CacheFlash Invalidation
- 3.4.1.5 Enabling and Disabling the Instruction Cache
- 3.4.1.6 Locking the Instruction Cache
- 3.4.2 Cache-ControlInstructions
- 1343.4.2.2 Data Cache Block Zero (dcbz)
- 1353.4.2.3 Data Cache Block Store (dcbst)
- 3.4.2.4 Data Cache Block Flush (dcbf)
- 3.4.2.5 Data Cache Block Invalidate (dcbi)
- 1363.5 Cache Operations
- 1383.5.2 Cache Flush Operations
- 1393.6 L1 Caches and 60x Bus Transactions
- 1403.6.1 Read Operations and the MEI Protocol
- 1413.6.2 Bus Operations Caused by Cache-ControlInstructions
- 1423.6.3 Snooping
- 1433.6.4 Snoop Response to 60x Bus Transactions
- 1453.6.5 Transfer Attributes
- 1473.7 MEI State Transactions
1514. Exceptions
- 1524.1 PowerPC 750GX Microprocessor Exceptions
- 1534.2 Exception Recognition and Priorities
- 1564.3 Exception Processing
- 1574.3.2 Machine Status Save/Restore Register 1 (SRR1)
- 1584.3.3 Machine State Register (MSR)
- 1604.3.4 Enabling and Disabling Exceptions
- 4.3.5 Steps for Exception Processing
- 1614.3.6 Setting MSR[RI]
- 4.3.7 Returning from an Exception Handler
- 1624.4 Process Switching
- 4.5 Exception Definitions
- 1634.5.1 System Reset Exception (0x00100)
- 1644.5.1.1 Soft Reset
- 4.5.1.2 Hard Reset
- 1674.5.2 Machine-CheckException (0x00200)
- 1684.5.2.1 Machine-CheckException Enabled (MSR[ME] = 1)
- 1694.5.2.2 Checkstop State (MSR[ME] = 0)
- 4.5.3 DSI Exception (0x00300)
- 4.5.4 ISI Exception (0x00400)
- 4.5.5 External Interrupt Exception (0x00500)
- 1704.5.6 Alignment Exception (0x00600)
- stmw
- 4.5.7 Program Exception (0x00700)
- 1714.5.8 Floating-PointUnavailable Exception (0x00800)
- 4.5.9 Decrementer Exception (0x00900)
- 4.5.10 System Call Exception (0x00C00)
- 4.5.11 Trace Exception (0x00D00)
- 4.5.12 Floating-PointAssist Exception (0x00E00)
- 1724.5.13 Performance-MonitorInterrupt (0x00F00)
- 1734.5.14 Instruction Address Breakpoint Exception (0x01300)
- 4.5.15 System Management Interrupt (0x01400)
- 1744.5.16 Thermal-ManagementInterrupt Exception (0x01700)
- 1754.5.17 Data Address Breakpoint Exception
- 4.5.17.1 Data Address Breakpoint Register (DABR)
- 4.5.18 Soft Stops
- 1764.5.19 Exception Latencies
- 4.5.20 Summary of Front-EndException Handling
- 1774.5.21 Timer Facilities
- 4.5.22 External Access Instructions
1795. Memory Management
- 5.1 MMU Overview
- 1815.1.1 Memory Addressing
- 5.1.2 MMU Organization
- 1865.1.3 Address-TranslationMechanisms
- 1875.1.4 Memory-ProtectionFacilities
- 1885.1.5 Page History Information
- 1895.1.6 General Flow of MMU Address Translation
- 5.1.6.1 Real-AddressingMode and Block-Address-TranslationSelection
- 1905.1.6.2 Page-Address-TranslationSelection
- 1925.1.7 MMU Exceptions Summary
- 193Notes:
- 1945.1.8 MMU Instructions and Register Summary
- 1955.2 Real-AddressingMode
- 1965.3 Block-AddressTranslation
- 5.4 Memory Segment Model
- 1975.4.1.1 Referenced Bit
- lswx
- 1985.4.1.2 Changed Bit
- 5.4.1.3 Scenarios for Referenced and Changed Bit Recording
- 1995.4.2 Page Memory Protection
- 5.4.3 TLB Description
- 5.4.3.1 TLB Organization
- 2015.4.3.2 TLB Invalidation
- 2025.4.4 Page-Address-TranslationSummary
- 2045.4.5 Page Table-SearchOperation
- 2075.4.6 Page Table Updates
- 5.4.7 Segment Register Updates
2096. Instruction Timing
- 6.1 Terminology and Conventions
- 2116.2 Instruction Timing Overview
- 2156.3 Timing Considerations
- 2166.3.2 Instruction Fetch Timing
- 2176.3.2.1 Cache Arbitration
- 6.3.2.2 Cache Hit
- 2226.3.2.3 Cache Miss
- 2246.3.2.4 L2 Cache Access Timing Considerations
- 6.3.2.5 Instruction Dispatch and Completion Considerations
- 6.3.2.6 Rename Register Operation
- 2256.4 Execution-UnitTimings
- 2266.4.1.1 Branch Folding
- 2276.4.1.2 Branch Instructions and Completion
- 2286.4.1.3 Branch Prediction and Resolution
- 231mulhw
- 2326.4.2 Integer Unit Execution Timing
- 6.4.3 Floating-PointUnit Execution Timing
- fdivs
- fdiv
- mtfsb0
- mtfsb1
- mtfsfi
- mffs
- 6.4.4 Effect of Floating-PointExceptions on Performance
- 2336.4.5 Load/Store Unit Execution Timing
- 6.4.6 Effect of Operand Placement on Performance
- 2346.4.7 Integer Store Gathering
- 6.4.8 System Register Unit Execution Timing
- 2356.5 Memory Performance Considerations
- 2366.6 Instruction Scheduling Guidelines
- 2376.6.1 Branch, Dispatch, and Completion-UnitResource Requirements
- 6.6.1.1 Branch-ResolutionResource Requirements
- 6.6.1.2 Dispatch-UnitResource Requirements
- 6.6.1.3 Completion-UnitResource Requirements
- 2386.7 Instruction Latency Summary
2497. Signal Descriptions
- 2507.1 Signal Configuration
- 2517.2 Signal Descriptions
- 2527.2.1.2 Bus Grant (BG)—Input
- 7.2.1.3 Address Bus Busy (ABB)
- 2537.2.2 Address Transfer Start Signals
- 7.2.2.1 Transfer Start (TS)
- 2547.2.3 Address Transfer Signals
- 7.2.3.1 Address Bus (A[0–31])
- 2557.2.3.2 Address-BusParity (AP[0–3])
- 7.2.4 Address Transfer Attribute Signals
- 2567.2.4.1 Transfer Type (TT[0–4])
- 2587.2.4.2 Transfer Size (TSIZ[0–2])—Output
- 2597.2.4.3 Transfer Burst (TBST)
- 2607.2.4.4 Cache Inhibit (CI)—Output
- 7.2.4.5 Write-Through (WT)—Output
- 2617.2.4.6 Global (GBL)
- 2627.2.5 Address Transfer Termination Signals
- 7.2.5.1 Address Acknowledge (AACK)—Input
- 2637.2.5.2 Address Retry (ARTRY)
- 2647.2.6 Data-BusArbitration Signals
- 7.2.6.1 Data-BusGrant (DBG)—Input
- 2657.2.6.2 Data-Bus Write-Only(DBWO)
- 7.2.6.3 Data Bus Busy (DBB)
- 2667.2.7 Data-TransferSignals
- 7.2.7.1 Data Bus (DH[0–31], DL[0–31])
- 2677.2.7.2 Data-BusParity (DP[0–7])
- 2687.2.7.3 Data Bus Disable (DBDIS)—Input
- 7.2.8 Data-TransferTermination Signals
- 7.2.8.1 Transfer Acknowledge (TA)—Input
- 269Warning
- 7.2.8.2 Data Retry (DRTRY)—Input
- 7.2.8.3 Transfer Error Acknowledge (TEA)—Input
- 2707.2.9 System Status Signals
- 7.2.9.1 Interrupt (INT)— Input
- 7.2.9.2 System Management Interrupt (SMI)—Input
- 2717.2.9.3 Machine-CheckInterrupt (MCP)—Input
- 7.2.9.4 Checkstop Input (CKSTP_IN)—Input
- 7.2.9.5 Checkstop Output (CKSTP_OUT)—Output
- 2727.2.10 Reset Signals
- 7.2.10.1 Hard Reset (HRESET)—Input
- 7.2.10.2 Soft Reset (SRESET)—Input
- 2737.2.11 Processor Status Signals
- 7.2.11.1 Quiescent Request (QREQ)—Output
- 7.2.11.2 Quiescent Acknowledge (QACK)—Input
- 7.2.11.3 Reservation (RSRV)—Output
- 2747.2.11.4 Time Base Enable (TBEN)—Input
- 7.2.11.5 TLB Invalidate Synchronize (TLBISYNC)—Input
- 7.2.12 Processor Mode Selection Signals
- 2757.2.13 I/O Voltage Select Signals
- 7.2.14 Test Interface Signals
- 7.2.14.1 IEEE 1149.1a-1993Interface Description
- 7.2.14.2 LSSD_MODE
- 2767.2.14.3 L1_TSTCLK
- 7.2.14.4 L2_TSTCLK
- 7.2.14.5 BVSEL
- 7.2.15 Clock Signals
- 2777.2.15.1 System Clock (SYSCLK)—Input
- 7.2.15.2 Clock Out (CLK_OUT)—Output
- 7.2.15.3 PLL Configuration (PLL_CFG[0:4])—Input
- 2787.2.15.4 PLL Range (PLL_RNG[0:1])—Input
- 7.2.16 Power and Ground Signals
2798. Bus Interface Operation
- 2808.1 Bus Interface Overview
- 2818.1.1 Operation of the Instruction and Data L1 Caches
- 2828.1.2 Operation of the Bus Interface
- 8.1.3 Bus Signal Clocking
- System Implementation Note:
- 8.1.4 Optional 32-BitData Bus Mode
- 2838.1.5 Direct-StoreAccesses
- 2848.2 Memory-AccessProtocol
- 2858.2.1 Arbitration Signals
- 2868.2.2 Miss-under-Miss
- 2878.2.2.1 Miss-under-Missand System Performance
- 2908.3 Address-BusTenure
- 2928.3.2 Address Transfer
- 2948.3.2.1 Address-BusParity
- 8.3.2.2 Address Transfer Attribute Signals
- 2958.3.2.3 Burst Ordering During Data Transfers
- 2968.3.2.4 Effect of Alignment in Data Transfers
- 3008.3.2.5 Alignment of External Control Instructions
- 8.3.3 Address Transfer Termination
- 3018.4 Data-BusTenure
- 3028.4.1.1 Using the DBB Signal
- 3038.4.2 Data-Bus Write-Only
- 8.4.3 Data Transfer
- 8.4.4 Data-TransferTermination
- 3048.4.4.1 Normal Single-BeatTermination
- 3078.4.4.2 Data-TransferTermination Due to a Bus Error
- 3088.4.5 Memory Coherency—MEIProtocol
- 3098.5 Timing Examples
- 3168.6 Optional Bus Configuration
- 3188.6.2 No-DRTRYMode
- 3198.7 Processor State Signals
- 8.8 IEEE 1149.1a-1993Compliant Interface
- 3208.9 Using Data-Bus Write-Only
3239. L2 Cache
- 9.1 L2 Cache Overview
- 9.2 L2 Cache Operation
- 328dcbst)
- dcbi)
- sync)
- 3299.3 L2 Cache Control Register (L2CR)
- 9.4 L2 Cache Initialization
- 9.5 L2 Cache Global Invalidation
- 3309.6 L2 Cache Used as On-ChipMemory
- 3319.6.1.1 Loading the Locked L2 Cache
- 9.6.1.2 Locked Cache Operation
- 3329.7 Data-Onlyand Instruction-OnlyModes
- 9.8 L2 Cache Test Features and Methods
- 3339.9 L2 Cache Timing
33510. Power and Thermal Management
- 10.1 Dynamic Power Management
- 10.2 Programmable Power Modes
- 33710.2.1 Power Management Modes
- 10.2.1.1 Full On Mode
- 10.2.1.2 Doze Mode
- 10.2.1.3 Nap Mode
- 33910.2.1.4 Sleep Mode
- 10.2.1.5 Dynamic Power Reduction
- 34010.3 750GX Dual PLL Feature
- 34110.3.2 Configuration Restriction on Frequency Transitions
- 34210.3.3 Dual PLL Implementation
- 34310.4 Thermal Assist Unit
- 34410.4.2 Thermal Assist Unit Operation
- 34510.4.2.1 TAU Single-ThresholdMode
- 34610.4.2.2 TAU Dual-ThresholdMode
- 10.4.2.3 750GX Junction Temperature Determination
- 34710.5 Instruction-CacheThrottling
34911. Performance Monitor and System Related Features
- 11.1 Performance-MonitorInterrupt
- 35011.2 Special-PurposeRegisters Used by Performance Monitor
- 35111.2.1 Performance-MonitorRegisters
- 11.2.1.1 Monitor Mode Control Register 0 (MMCR0)
- 11.2.1.2 User Monitor Mode Control Register 0 (UMMCR0)
- 11.2.1.3 Monitor Mode Control Register 1 (MMCR1)
- 11.2.1.4 User Monitor Mode Control Register 1 (UMMCR1)
- 11.2.1.5 Performance-MonitorCounter Registers (PMCn)
- 35411.2.1.6 User Performance-MonitorCounter Registers (UPMC1–UPMC4)
- 35511.3 Event Counting
- 35611.4 Event Selection
- 11.5 Notes
- 35711.6 Debug Support
- 11.7 JTAG/COP Functions
- 35911.8 Resets
- 36011.8.3 Reset Sequence
- 36111.9 Checkstops
- 36211.9.3 Open-Collector-DriverStates during Checkstop
- 11.9.4 Vacancy Slot Application
- 36311.10 750GX Parity
- 36411.10.1 Parity Control and Status
- 11.10.2 Enabling Parity Error Detection
- 11.10.3 Parity Errors
365Acronyms and Abbreviations
369Index
- 371H, I, J, K
- 375U, V, W
377Revision Log

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