IBM 750GL, 750GX 2.3.2 Addressing Modes, 2.3.2.2 Memory Operands, 2.3.2.1 Memory Addressing, 2.3.1.4 Reserved Instruction Class

User’s Manual

IBM PowerPC 750GX and 750GL RISC Microprocessor

2.3.1.4 Reserved Instruction Class

Reserved instructions are allocated to specific implementation-dependent purposes not defined by the PowerPC Architecture. Attempting to execute an unimplemented reserved instruction invokes the illegal instruction error handler (a program exception). See Section 4.5.7 on page 170 for information about illegal and invalid instruction exceptions.

The PowerPC Architecture defines four types of reserved instructions:

•Instructions in the POWER architecture not part of the PowerPC UISA. For details on POWER architec- ture incompatibilities and how they are handled by PowerPC processors, see Appendix B, “POWER Architecture Cross Reference” in the PowerPC Microprocessor Family: The Programming Environments Manual.

•Implementation-specific instructions required for the processor to conform to the PowerPC Architecture (none of these are implemented in the 750GX)

•All other implementation-specific instructions

•Architecturally-allowed extended opcodes

2.3.2 Addressing Modes

This section provides an overview of conventions for addressing memory and for calculating effective addresses as defined by the PowerPC Architecture for 32-bit implementations. For more detailed information, see “Conventions” in Chapter 4, “Addressing Modes and Instruction Set Summary” of the PowerPC Microprocessor Family: The Programming Environments Manual.

2.3.2.1 Memory Addressing

A program references memory using the effective (logical) address computed by the processor when it executes a memory-access or branch instruction or when it fetches the next sequential instruction. Bytes in memory are numbered consecutively starting with zero. Each number is the address of the corresponding byte.

2.3.2.2 Memory Operands

Memory operands can be bytes, half words, words, or double words, or, for the load/store multiple and load/store string instructions, a sequence of bytes or words. The address of a memory operand is the address of its first byte (that is, of its lowest-numbered byte). Operand length is implicit for each instruction. The PowerPC Architecture supports both big-endian and little-endian byte ordering. The default byte and bit ordering is big-endian. See “Byte Ordering” in Chapter 3, “Operand Conventions” of the PowerPC Microprocessor Family: The Programming Environments Manual for more information about big and little-endian byte ordering.

The operand of a single-register memory-access instruction has a natural alignment boundary equal to the operand length. In other words, the “natural” address of an operand is an integral multiple of the operand length. A memory operand is said to be aligned if it is aligned at its natural boundary; otherwise, it is misaligned.

For a detailed discussion about memory operands, see Chapter 3, “Operand Conventions” of the PowerPC Microprocessor Family: The Programming Environments Manual.

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